LMX2471SLEX National Semiconductor, LMX2471SLEX Datasheet - Page 35

• Manufacturer Part Number: LMX2471SLEX
• Description: IC PLL LP 3.6GHZ/1.7GHZ 24-CSP
• Manufacturer: National Semiconductor
• Type: PLL Frequency Synthesizer, Delta Sigmar

Specifications of LMX2471SLEX

• Pll: Yes with Bypass
• Input: CMOS
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:3
• Differential - Input:output: Yes/No
• Frequency - Max: 3.6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-Laminate UTCSP
• Frequency-max: 3.6GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LMX2471SLEXTR

R8
Programming Description
2.9 R8 REGISTER
The R8 Register controls some additional bits that may be useful in optimizing phase noise, lock time, and spurs.
2.9.1 CPUD[2:0] -- Charge Pump User Definition
This bit allows the user to choose from several different modes in the charge pump. The charge pump current is unaffected, but
the fractional spurs and phase noise are impacted by a few dB. In some designs, particularly if the loop bandwidth is wide and
a 4th order delta-sigma engine is used, small spurs may appear at a fraction of where the first fractional spur should appear. In
other designs, these sub-fractional spurs are not present. The user needs to use this adjustment to make these sub-fractional
spurs go away, while still getting the best phase noise possible.
2.9.2 PDCP[1:0] -- Power Drive for Charge Pump
If this bit is enabled, the Fastlock current can be doubled during Fastlock. The charge pump current in steady state is unaffected.
States 0 and 1 should never be used.
2.9.3 DITH[1:0] -- Dithering Control
Dithering is a technique used to spread out the spur energy. Enabling dithering can reduce the main fractional spurs, but can also
give rise to a family of smaller spurs. Whether dithering helps or hurts is application specific. Enabling the dithering may also
increase the phase noise. In most cases where the fractional numerator is zero, dithering usually degrades performance.
Dithering tends to be most beneficial in applications where there is insufficient filtering of the spurs. This often occurs when the
loop bandwidth is very wide or a higher order delta-sigma modulator is used. Dithering tends not to impact the main fractional
spurs much, but has a much larger inpact on the sub-fractional spurs. If it is decided that dithering will be used, best results will
be obtained when the fractional denominator is at least 1000.
23
0
CPUD
22
0
0
1
2
3
4
5
6
7
21
0
20
0
PDCP
0
1
2
3
DITH
19
0
1
2
3
DITH
[1:0]
18
Mode Name
Maximum
Reserved
Reserved
Reserved
Reserved
Reserved
Minimum
Nominal
17
0
16
0
(Continued)
15
DATA[19:0]
0
14
0
13
0
35
Phase Noise
12
0
Medium
Worst
Best
N/A
N/A
N/A
N/A
N/A
11
Fastlock Charge Pump Current
PDCP
[1:0]
Double Fastlock Current
10
Dithering Mode Used
Dithering Disabled
Dithering Enabled
9
0
Reserved
Reserved
Disabled
Reserved
Reserved
8
0
7
CPUD
[2:0]
6
Sub-Fractional Spurs
5
Medium
4
0
Worst
Best
N/A
N/A
N/A
N/A
N/A
C3
3
1
C2
2
1
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C1
1
1
C0
0
1