LMX2471SLEX National Semiconductor, LMX2471SLEX Datasheet - Page 34

• Manufacturer Part Number: LMX2471SLEX
• Description: IC PLL LP 3.6GHZ/1.7GHZ 24-CSP
• Manufacturer: National Semiconductor
• Type: PLL Frequency Synthesizer, Delta Sigmar

Specifications of LMX2471SLEX

• Pll: Yes with Bypass
• Input: CMOS
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:3
• Differential - Input:output: Yes/No
• Frequency - Max: 3.6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-Laminate UTCSP
• Frequency-max: 3.6GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LMX2471SLEXTR

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REGISTER
Programming Description
2.8 R7 REGISTER
2.8.1 Fractional Numerator Determination { RF_FN2[9:0], RF_FN[11:0], FDM }
In the case that the FDM bit is 0, then the part operates in 12-bit fractional mode, and the RF_FN2 bits become don’t care bits.
When the FDM is set to 1, the part operates in 22-bit mode and the fractional numerator is expanded from 12 to 22-bits.
2.8.2 Fractional Denominator Determination { RF_FD2[9:0], RF_FD[11:0], FDM }
In the case that the FDM bit is 0, then the part is operates in the 12-bit fractional mode, and the RF_FD2 bits become don’t care
bits. When the FDM is set to 1, the part operates in 22-bit mode and the fractional denominator is expanded from 12 to 22-bits.
Numerator
Denominator
Fractional
R7
4194303
Fractional
4194303
4095
4096
4095
4096
...
...
0
1
...
...
0
1
23
0
1
.
22
0
1
.
21
0
1
.
( These bits only apply in 22- bit mode)
0
1
.
In 12- bit mode, these are don’t care.
( These bits only apply in 22- bit mode)
In 12- bit mode, these are don’t care.
20
these bits should be all set to 0.
0
1
.
In 22- bit mode, for N
these bits should be all set to 0.
RF_FD2[9:0]
0
1
In 22- bit mode, for N
.
19
0
1
.
0
1
.
RF_FN2[9:0]
18
RF_FD2[9:0]
0
1
.
0
1
.
17
(Continued)
0
1
.
0
1
.
16
<
0
1
.
DATA[19:0]
4096,
<
15
0
1
.
4096,
0
1
.
14
0
1
.
34
13
0
1
.
0
1
.
12
1
1
.
1
1
.
11
0
0
1
0
1
.
.
0
0
1
0
1
.
.
RF_FN2[9:0]
10
0
0
1
0
1
.
.
0
0
1
0
1
.
.
0
0
1
0
1
.
.
9
0
0
1
0
1
.
.
0
0
1
0
1
8
.
.
0
0
1
0
1
.
.
7
0
0
1
0
1
.
.
RF_FN[11:0]
0
0
1
0
1
.
.
RF_FD[11:0]
6
0
0
1
0
1
.
.
0
0
1
0
1
.
.
5
0
0
1
0
1
.
.
0
0
1
0
1
.
.
4
0
0
1
0
1
.
.
0
0
1
0
1
.
.
C3
3
1
0
0
1
0
1
.
.
0
0
1
0
1
.
.
C2
0
0
1
0
1
2
1
.
.
0
0
1
0
1
.
.
0
0
1
0
1
0
0
1
0
1
.
.
C1
.
.
1
0
0
1
1
0
1
0
1
1
0
1
.
.
.
.
C0
0
1