LMX2471SLEX National Semiconductor, LMX2471SLEX Datasheet

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LMX2471SLEX

Manufacturer Part Number
LMX2471SLEX
Description
IC PLL LP 3.6GHZ/1.7GHZ 24-CSP
Manufacturer
National Semiconductor
Type
PLL Frequency Synthesizer, Delta Sigmar
Datasheet

Specifications of LMX2471SLEX

Pll
Yes with Bypass
Input
CMOS
Output
CMOS
Number Of Circuits
1
Ratio - Input:output
3:3
Differential - Input:output
Yes/No
Frequency - Max
3.6GHz
Divider/multiplier
Yes/Yes
Voltage - Supply
2.25 V ~ 2.75 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-Laminate UTCSP
Frequency-max
3.6GHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
LMX2471SLEXTR
© 2003 National Semiconductor Corporation
LMX2471
3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz
Integer-N PLL
General Description
The LMX2471 is a low power, high performance delta-sigma
fractional-N PLL with an auxiliary integer-N PLL. The device
is fabricated using National Semiconductor’s advanced BiC-
MOS process.
With delta-sigma architecture, fractional spur compensation
is achieved with noise shaping capability of the delta-sigma
modulator and the inherent low pass filtering of the PLL loop
filter. Fractional spurs at lower frequencies are pushed to
higher frequencies outside the loop bandwidth. Unlike ana-
log compensation, the digital feedback techniques used in
the LMX2471 are highly resistant to changes in temperature
and variations in wafer processing. With delta-sigma archi-
tecture, the ability to push close in spur and phase noise
energy to higher frequencies is a direct function of the modu-
lator order. The higher the order, the more this energy can be
spread to higher frequencies. The LMX2471 has a program-
mable modulator up to order four, which allows the designer
to select the optimum modulator order to fit the phase noise,
spur, and lock time requirements of the system.
Programming is fast and simple. Serial data is transferred
into the LMX2471 via a three line MICROWIRE interface
(Data, Clock, Load Enable). Nominal supply voltage is 2.5 V.
The LMX2471 features a typical current consumption of 5.6
mA at 2.5 V. The LMX2471 is available in a 24 lead 3.5 X 4.5
X 0.6 mm package.
Functional Block Diagram
DS200721
Features
n Low in-band phase noise and low fractional spurs
n 12 bit or 22 bit selectable fractional modulus
n Up to 4th order programmable delta-sigma modulator
n Enhanced Anti-Cycle Slip Fastlock Circuitry
n Digital lock detect output
n Prescalers allow wide range of N values
n Crystal Reference Frequency up to 110 MHz
n On-chip crystal reference frequency doubler.
n Phase Comparison Frequency up to 50 MHz
n Hardware and software power-down control
n Ultra low consumption: I
Applications
n Cellular Phones and Base Stations
n Applications requiring fine frequency resolution
n Satellite and Cable TV Tuners
n WLAN Standards
Fastlock
Cycle slip reduction
Integrated timeout counters
RF PLL: 16/17/20/21
IF PLL: 8/9 or 16/17
CC
= 5.6 mA (typical)
20072101
November 2003
www.national.com

Related parts for LMX2471SLEX

LMX2471SLEX Summary of contents

Page 1

... Integer-N PLL General Description The LMX2471 is a low power, high performance delta-sigma fractional-N PLL with an auxiliary integer-N PLL. The device is fabricated using National Semiconductor’s advanced BiC- MOS process. With delta-sigma architecture, fractional spur compensation is achieved with noise shaping capability of the delta-sigma modulator and the inherent low pass filtering of the PLL loop filter ...

Page 2

Connection Diagram Pin Descriptions Pin # Pin I/O Name 1 CPoutRF O RF charge pump output. 2 GND - Ground 3 GND - RF Ground 4 GND - Ground for RF PLL digital circuitry. 5 FinRF I RF prescaler input. ...

Page 3

Absolute Maximum Ratings Parameter Power Supply Voltage Voltage on any pin with GND = Storage Temperature Range Lead Temperature (Solder 4 sec.) Recommended Operating Conditions Parameter Power Supply Voltage (Note 1) Operating Temperature Note 1: “Absolute Maximum ...

Page 4

Electrical Characteristics Symbol Parameter RF SYNTHESIZER PARAMETERS I SINK RF Charge Pump Sink CPoutRF Current I TRI RF Charge Pump CPoutRF TRI-STATE Current Magnitude I %MIS RF CP Sink vs. CP Source CPoutRF Mismatch Current vs. ...

Page 5

Electrical Characteristics Symbol Parameter DIGITAL INTERFACE (DATA, CLK, LE, EN, ENRF, Ftest/LD, FLoutRF, FLoutIF) V Low-Level Output Voltage OL MICROWIRE INTERFACE TIMING T Data to Clock Set Up Time CS T Data to Clock Hold Time CH T Clock Pulse ...

Page 6

Typical Performance Characteristics : Sensitivity www.national.com (Note Counter Sensitivity T = 25˚ Counter Sensitivity 20072145 20072146 ...

Page 7

Typical Performance Characteristics : Sensitivity (Note Counter Sensitivity T = 25˚ Counter Sensitivity (Continued) 20072147 20072148 www.national.com ...

Page 8

Typical Performance Characteristics : Sensitivity www.national.com (Note 6) OSCin Counter Sensitivity OSC 25˚ OSCin Counter Sensitivity OSC 2 (Continued) 20072149 20072150 ...

Page 9

Typical Performance Characteristic : FinRF Input Impedance Frequency (MHz) 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 FinRF Input Impedance (V =2 (Note 5) Real (Ohms) 389.9 270.8 160.4 95.7 ...

Page 10

Typical Performance Characteristic : FinIF Input Impedance Freqeuncy (MHz) 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 www.national.com FinIF Input Impedance (V =2 (Note 5) Real (Ohms) 377.4 ...

Page 11

Typical Performance Characteristic : OSCin Input Impedance Frequency (MHz 100 110 OSCin Input Impedance (V =2 (Note 5) Real (Ohms) Imaginary (Ohms) 2200 -4700 710 -2700 229 ...

Page 12

Typical Performance Characteristics : Currents www.national.com (Note 6) Total Current Consumption OSC=0 Powerdown Current EN = LOW 12 20072159 20072161 ...

Page 13

Typical Performance Characteristics : Currents (Note 6) RF Charge Pump Current V = 2.5 Volts CC IF Charge Pump Current V = 2.5 Volts CC 13 (Continued) 20072167 20072165 www.national.com ...

Page 14

Typical Performance Characteristics : Currents Note 5: The input impedance of the FinRF, FinIF, and OSCin pins does not change significantly with voltage or temperature. The impedance of the FinRF and FinIF pins also does not change much when the ...

Page 15

Bench Test Setups CHARGE PUMP CURRENT MEASUREMENT PROCEDURE The above block diagram shows the test procedure for test- ing the RF and IF charge pumps. These tests include abso- lute current level, mismatch, and leakage. In order to mea- sure ...

Page 16

Bench Test Setups (Continued) SENSITIVITY MEASUREMENT PROCEDURE Frequency Input Pin DC Blocking Capacitor OSCin 1000 pF FinRF 47 pF FinIF 100 pF Sensitivity is defined as the power level limits beyond which the output of the counter being tested is ...

Page 17

Bench Test Setups (Continued) INPUT IMPEDANCE MEASUREMENT PROCEDURE The above block diagram shows the test procedure measur- ing the input impedance for the LMX2471. This applies to the FinRF, FinIF, and OSCin pins and is measured ohm ...

Page 18

... GENERAL The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency synthe- sizer such as the National Semiconductor LMX2471, a volt- age controlled oscillator (VCO), and a passive loop filter. The frequency synthesizer includes a phase detector, current mode charge pump, as well as programmable reference [R] and feedback [N] frequency dividers ...

Page 19

Functional Description 1.4 DIGITAL LOCK DETECT OPERATION The RF PLL digital lock detect circuitry compares the differ- ence between the phase of the inputs of the phase detector generated delay of 10 nS. To enter the locked ...

Page 20

Functional Description 1.5 PCB LAYOUT CONSIDERATIONS Power Supply Pins For these pins recommended that these be filtered by taking a series 18 ohm resistor and then placing two capacitors shunt to ground, thus creating a low pass filter. ...

Page 21

Functional Description 1.6.1 Determining the Loop Gain Multiplier, K The loop bandwidth multiplier needed in order to de- termine the theoretical impact of fastlock/CSR on the loop bandwidth and also which resistor should be switched in parallel with ...

Page 22

Functional Description 1.6.4 RF PLL Fastlock Reference Table and Example The table below shows most of the trade-offs involved in choosing a steady-state charge pump current (RF_CPG), Parameter Advantages to Choosing Smaller RF_CPG 1. Allows capacitors in loop filter to ...

Page 23

Functional Description 1.6.5 Capacitor Dielectric Considerations for Lock Time The LMX2471 has a high fractional modulus and high charge pump gain for the lowest possible phase noise. One consideration is that the reduced N value and higher charge pump may ...

Page 24

Programming Description 2.0 GENERAL PROGRAMMING INFORMATION The descriptions below describe the 24-bit data registers loaded through the MICROWIRE Interface. These data registers are used to program the R counter, the N counter, and the internal mode control latches. The data ...

Page 25

25 www.national.com ...

Page 26

Programming Description 2.1 R0 REGISTER Note that this register has only one control bit. The reason for this is that it enables the N counter value to be changed with a single write statement to the PLL. REGISTER 23 22 ...

Page 27

Programming Description 2.2 R1 REGISTER REGISTER DATA[19:0] ( Except for the RF_N Register, which is [22: RF_PD 1 RF_R[5:0] 2.2.1 RF_FD[11: PLL Fractional Denominator The function of these bits are described in ...

Page 28

Programming Description 2.3 R2 REGISTER REGISTER DATA[19:0] ( Except for the RF_N Register, which is [22: IF_PD IF_P IF_CPG 2.3.1 IF_N[16: Divider Value The IF N divider is a classical dual modulus ...

Page 29

Programming Description 2.4 R3 REGISTER REGISTER DATA[19:0] ( Except for the RF_N Register, which is [22: RF_CPG[3:0] 2.4.1 IF_R[14: Divider Value For the IF R divider, the R value ...

Page 30

Programming Description 2.5 R4 REGISTER This register controls the conditions for the RF PLL in Fastlock. REGISTER DATA[19:0] ( Except for the RF_N Register, which is [22: CSR[1:0] RF_CPF[3:0] 2.5.1 RF_TOC -- RF ...

Page 31

Programming Description 2.5.3 RF_CSR[1: Cycle Slip Reduction CSR controls the operation of the Cycle Slip Reduction Circuit. This circuit can be used to reduce the occurrence of phase detector cycle slips. Note that the Fastlock charge pump current, ...

Page 32

Programming Description 2.7 R6 REGISTER REGISTER DATA[19:0] ( Except for the RF_N Register, which is [22: RF_ CPT 2.7.1 MUX[3:0] Frequency Out & Lock Detect MUX These ...

Page 33

Programming Description 2.7.5 FM[1:0] -- Fractional Mode Determines the order of the delta-sigma modulator. Higher order delta-sigma modulators reduce the spur levels closer to the carrier by pushing this noise to higher frequency offsets from the carrier. In general, the ...

Page 34

Programming Description 2.8 R7 REGISTER REGISTER RF_FD2[9:0] 2.8.1 Fractional Numerator Determination { RF_FN2[9:0], RF_FN[11:0], FDM } In the case that the FDM bit is 0, then the part operates in 12-bit fractional mode, and ...

Page 35

Programming Description 2.9 R8 REGISTER DITH [1:0] The R8 Register controls some additional bits that may be useful in optimizing phase noise, lock time, and spurs. 2.9.1 CPUD[2:0] -- ...

Page 36

... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted Ultra Thin Chip Scale Package (SLE) For Tape and Reel (2500 Units per Reel) Order Number LMX2471SLEX NS Package Number SLE24A 2. A critical component is any component of a life support device or system whose failure to perform ...

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