LMX2471SLEX National Semiconductor, LMX2471SLEX Datasheet - Page 21

• Manufacturer Part Number: LMX2471SLEX
• Description: IC PLL LP 3.6GHZ/1.7GHZ 24-CSP
• Manufacturer: National Semiconductor
• Type: PLL Frequency Synthesizer, Delta Sigmar

Specifications of LMX2471SLEX

• Pll: Yes with Bypass
• Input: CMOS
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:3
• Differential - Input:output: Yes/No
• Frequency - Max: 3.6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-Laminate UTCSP
• Frequency-max: 3.6GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LMX2471SLEXTR

Functional Description
1.6.1 Determining the Loop Gain Multiplier, K
The loop bandwidth multiplier, K, is needed in order to de-
termine the theoretical impact of fastlock/CSR on the loop
bandwidth and also which resistor should be switched in
parallel with the loop filter resistor R2. K = K_K · K_Fcomp
where K is the loop gain multiplier K_K is the ratio of the
Fastlock charge pump current to the steady state charge
pump current. Note that this should always be greater than
or equal to one. K_Fcomp is the ratio of the Fastlock com-
parison frequency to the steady state comparison frequency.
If this ratio is less than one, this implies that the CSR is being
used.
1.6.2 Determining the Theoretical Lock Time
Improvement and Fastlock Resistor, R2’
When using fastlock, it is necessary to switch in a resistor
R2’, in parallel with R2 in order to keep the loop filter opti-
mized and maintain the same phase margin. After the PLL
has achieved a frequency that is sufficiently close to the
desired frequency, the resistor R2’ is disengaged and the
charge pump current is and comparison frequency are re-
turned to normal. Of special concern is the glitch that is
caused when the resistor R2’ is disengaged. This glitch can
take up a significant portion of the lock time. The LMX2471
has enhanced switching circuitry to minimize this glitch and
therefore improve the lock time.
The change in loop bandwidth is dependent upon the loop
gain multiplier, K, as determined in section 4. The theoretical
improvement in lock time is given below, but the actual
improvement will be less than this due to the glitch that is
caused by disengaging Fastlock. The theoretical improve-
ment is given to show an upper bound on what improvement
is possible with Fastlock. In the case that K
the CSR is being engaged and that the theoretical lock time
will be degraded. However, since this mode reduces or
eliminates cycle slipping, the actual lock time may be better
in cases where the loop bandwidth is small relative to the
comparison frequency. Realize that the theoretical lock time
multiplier does not account for the fastlock/CSR disengage-
ment glitch, which is most severe for larger values of K.
* These modes of operation are generally not recommended
Multiplier, K
Loop Gain
16:1
32:1
1:8*
1:4*
1:2*
4:1
8:1
Loop Bandwidth
Multiplier
0.35
0.50
0.71
2.00
2.83
4.00
5.66
20072140
R2’ Value
R2/1.00
R2/1.83
R2/3.00
R2/4.65
open
open
open
(Continued)
<
1, this implies
Lock Time
Multiplier
x 2.828
x 2.000
x 1.414
x 0.500
x 0.354
x 0.250
x 0.177
21
1.6.3 Using Fastlock and Cycle Slip Reduction (CSR)
to Avoid Cycle Slipping
In the case that the comparison frequency is very large ( i.e.
100 X ) of the loop bandwidth, cycle slipping may occur when
an instantaneous phase error is presented to the phase
detector. This can be reduced by increasing the loop band-
width during frequency acquisition, decreasing the compari-
son frequency during frequency acquisition, or some combi-
nation of the these. If increasing the loop bandwidth during
frequency acquisition is not sufficient to reduce cycle slip-
ping, the LMX2471 also has a routine to decrease the com-
parison frequency.
www.national.com