LMX2471SLEX National Semiconductor, LMX2471SLEX Datasheet - Page 20

• Manufacturer Part Number: LMX2471SLEX
• Description: IC PLL LP 3.6GHZ/1.7GHZ 24-CSP
• Manufacturer: National Semiconductor
• Type: PLL Frequency Synthesizer, Delta Sigmar

Specifications of LMX2471SLEX

• Pll: Yes with Bypass
• Input: CMOS
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:3
• Differential - Input:output: Yes/No
• Frequency - Max: 3.6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-Laminate UTCSP
• Frequency-max: 3.6GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LMX2471SLEXTR

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Functional Description
1.5 PCB LAYOUT CONSIDERATIONS
Power Supply Pins For these pins, it is recommended that
these be filtered by taking a series 18 ohm resistor and then
placing two capacitors shunt to ground, thus creating a low
pass filter. Although it makes sense to use large capacitor
values in theory, the ESR ( Equivalent Series Resistance ) is
greater for larger capacitors. For optimal filtering minimize
the sum of the ESR and theoretical impedance of the ca-
pacitor. It is therefore recommended to provide two capaci-
tors of very different sizes for the best filtering. 0.1 µF and
100 pF are typical values. The charge pump supply pins in
particular are vuvulnerablenerable to power supply noise.
High Frequency Input Pins, FinRF and FinIF The signal
path from the VCO to the PLL is the most sensitive and
challenging for board layout. It is generally recommended
that the VCO output go through a resistive pad and then
through a DC blocking capacitor before it gets to these high
frequency input pins. If the trace length is sufficiently short (
sary, but a series resistor of about 39 ohms is still recom-
mended to isolate the PLL from the VCO. The DC blocking
Note that if the charge pump current and cycle slip reduction circuitry are engaged in the same proportion, then it is not necessary
to switch in a Fastlock resistor and the loop filter will be optimized for both normal mode and Fastlock mode. For third and fourth
order filters which have problems with cycle slipping, this may prove to be the optimal choice of settings.
<
Keep Charge Pump Current the Same
1/10th of a wavelength ), then the pad may not be neces-
Decrease Charge Pump Current
Increase Charge Pump Current
Charge Pump Current
(Continued)
Classical Fastlock
Allows the loop bandwidth to be
increased. This has a frequency glitch
caused by switching the charge pump
currents, but there is no frequency glitch
caused by switching from fractional to
integer mode
Operation with No Fastlock
This mode represents using no Fastlock
It never makes sense to use a lower
charge pump current during Fastlock
than in the steady state.
Frequency the Same
Keep Comparison
20
capacitor should be chosen at least to be 100 pF. It may turn
out that the frequency in this trace is above the self-resonant
frequency of the capacitor, but since the input impedance of
the PLL tends to be capacitive, it actually be a benefit to
exceed the self-resonant frequency. The pad and the DC
blocking capacitor should be placed as close to the PLL as
possible
Complimentary High Frequency Pin, FinRF* These inputs
may be used to drive the PLL differentially, but it is very
common to drive the PLL in a single ended fashion. A shunt
capacitor should be placed at the FinRF* pin. The value of
this capacitor should be chosen such that the impedance,
including the ESR of the capacitor, is as close to an AC short
as possible at the operating frequency of the PLL. 100 pF is
a typical value.
1.6 FASTLOCK AND CYCLE SLIP REDUCTION
The LMX2471 has enhanced features for Fastlock and cycle
slip operation. The next several sections discuss the the
benefits of using both of these features. There are four
possible combinations that are possible, and these are
shown in the table below:
CSR/Fastlock Combination
Engaging the CSR does decrease the
loop bandwidth during frequency
acquisition, but may be necessary to
reduce cycle slipping. By also
increasing the charge pump current, this
can compensate for the reduce loop
bandwidth due to the CSR
CSR Only
This mode is not generally
recommended, but may reduce cycle
slipping in some applications. Although
the theoretical lock time is decreased,
due to the decreased loop bandwidth
during Fastlock, cycle slips can be
reduced or eliminated.
Decrease Comparison
Frequency (CSR)
(RF Side Only)