LMX2471SLEX National Semiconductor, LMX2471SLEX Datasheet - Page 30

• Manufacturer Part Number: LMX2471SLEX
• Description: IC PLL LP 3.6GHZ/1.7GHZ 24-CSP
• Manufacturer: National Semiconductor
• Type: PLL Frequency Synthesizer, Delta Sigmar

Specifications of LMX2471SLEX

• Pll: Yes with Bypass
• Input: CMOS
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:3
• Differential - Input:output: Yes/No
• Frequency - Max: 3.6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-Laminate UTCSP
• Frequency-max: 3.6GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LMX2471SLEXTR

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REGISTER
Programming Description
2.5 R4 REGISTER
This register controls the conditions for the RF PLL in Fastlock.
2.5.1 RF_TOC -- RF Time Out Counter and Control for FLoutRF Pin
The RF_TOC[13:0] word controls the operation of the RF Fastlock circuitry as well as the function of the FLoutRF output pin.
When this word is set to a value between 0 and 3, the RF Fastlock circuitry is disabled and the FLoutRF pin operates as a general
purpose CMOS TRI-STATE I/O. When RF_TOC is set to a value between 4 and 16383, the RF Fastlock mode is enabled and
the FLoutRF pin is utilized as the RF Fastlock output pin. The value programmed into the RF_TOC[13:0] word represents four
times the number of phase detector comparison cycles the RF synthesizer will spend in the Fastlock state.
2.5.2 RF_CPF -- RF PLL Fastlock Charge Pump Current
Specify the charge pump current for the Fastlock operation mode for the RF PLL. Note that the Fastlock charge pump current,
steady state current, and CSR control are all interrelated. Refer to section 4.0 for more details.
R4
RF_TOC[13:0]
16383
…
0
1
2
3
4
5
23
CSR[1:0]
RF_CPF [3:0]
22
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
21
RF_CPF[3:0]
Fastlock Mode
DATA[19:0] ( Except for the RF_N Register, which is [22:0] )
20
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Manual
19
18
17
(Continued)
16
Fastlock Period [CP events]
15
16383X2=32766
14
30
5X2 = 10
4X2 = 8
13
N/A
N/A
N/A
N/A
…
RF_TOC[13:0]
Fastlock Charge Pump Current (µA)
12
11
10
9
1000
1100
1200
1300
1400
1500
1600
100
200
300
400
500
600
700
800
900
8
Forces all fastlock conditions
FLoutRF Pin Functionality
7
6
High Impedance
Logic “0” State.
Logic “0” State
Logic “1” State
5
Fastlock
Fastlock
Fastlock
Fastlock
4
C3
3
0
C2
2
1
C1
1
1
C0
0
1