LMX2471SLEX National Semiconductor, LMX2471SLEX Datasheet - Page 31

• Manufacturer Part Number: LMX2471SLEX
• Description: IC PLL LP 3.6GHZ/1.7GHZ 24-CSP
• Manufacturer: National Semiconductor
• Type: PLL Frequency Synthesizer, Delta Sigmar

Specifications of LMX2471SLEX

• Pll: Yes with Bypass
• Input: CMOS
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:3
• Differential - Input:output: Yes/No
• Frequency - Max: 3.6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-Laminate UTCSP
• Frequency-max: 3.6GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LMX2471SLEXTR

REGISTER
Programming Description
2.5.3 RF_CSR[1:0] -- RF Cycle Slip Reduction
CSR controls the operation of the Cycle Slip Reduction Circuit. This circuit can be used to reduce the occurrence of phase
detector cycle slips. Note that the Fastlock charge pump current, steady state current, and CSR control are all interrelated. The
table below gives some rough guidelines. In the table below, f
of the PLL system. The rough guideline gives an idea of when it makes sense to use this cycle slip reduction based on the
steady-state conditions of the PLL system.
2.6 R5 REGISTER
2.6.1 IF_TOC[11:0] IF Timeout Counter for Fastlock
The IF_TOC word controls the operation of the IF Fastlock circuitry as well as the function of the FLoutIF output pin. When
IF_TOC is set to a value between 0 and 3, the IF Fastlock circuitry is disabled and the FLoutIF pin operates as a general purpose
CMOS TRI-STATE output. When IF_TOC is set to a value between 4 and 4095, the IF Fastlock mode is enabled and FLoutIF is
utilized as the IF Fastlock output pin. The value programmed into IF_TOC represents the number of phase comparison cycles that
the IF synthesizer will spend in the Fastlock state.
IF_TOC[11:0]
R5
CSR[1:0]
4095
…
0
1
2
3
4
0
1
2
3
23
0
22
0
Fastlock Mode
21
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
0
Manual
CSR State
Disabled
Enabled
Enabled
Enabled
20
0
DATA[19:0] ( Except for the RF_N Register, which is [22:0] )
19
0
18
0
Fastlock Period [Charge Pump Cycles]
17
0
(Continued)
Sample Rate Reduction Factor
16
0
15
4095
N/A
N/A
N/A
N/A
…
14
5
1/16
1/2
1/4
COMP
1
31
13
is the comparison frequency, and BW is the loop bandwidth
12
IF_TOC[11:0]
11
10
Forces IF charge pump current to 4 mA
9
100 x BW
200 x BW
8
FLoutIF Pin Functionality
7
f
f
Rough Guideline
COMP
COMP
High Impedance
6
Logic “0” State
Logic “0” State
Logic “1” State
<
<
Fastlock
Fastlock
Fastlock
5
f
f
<
>
COMP
COMP
100 x BW
400 x BW
4
C3
<
<
3
1
200 x BW
400 x BW
C2
2
0
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C1
1
0
C0
0
1