IDT82V3255TFG8 IDT, Integrated Device Technology Inc, IDT82V3255TFG8 Datasheet - Page 6

• Manufacturer Part Number: IDT82V3255TFG8
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG8

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG8

List of Tables
Table 1: Pin Description ............................................................................................................................................................................................. 13
Table 2: Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 17
Table 3: Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 18
Table 4: Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 19
Table 5: Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 21
Table 6: Input Clock Selection for T0 Path ................................................................................................................................................................ 22
Table 7: Input Clock Selection for T4 Path ................................................................................................................................................................ 22
Table 8: External Fast Selection ................................................................................................................................................................................ 22
Table 9: ‘n’ Assigned to the Input Clock ..................................................................................................................................................................... 23
Table 10: Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 23
Table 11: Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 24
Table 12: Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 24
Table 13: Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 25
Table 14: Conditions of Qualified Input Clocks Available for T0 & T4 Selection ......................................................................................................... 26
Table 15: Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 27
Table 16: T0 DPLL Operating Mode Control ............................................................................................................................................................... 28
Table 17: T4 DPLL Operating Mode Control ............................................................................................................................................................... 30
Table 18: Related Bit / Register in Chapter 3.9 ........................................................................................................................................................... 30
Table 19: Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 31
Table 20: Frequency Offset Control in Holdover Mode ............................................................................................................................................... 32
Table 21: Holdover Frequency Offset Read ................................................................................................................................................................ 32
Table 22: Related Bit / Register in Chapter 3.10 ......................................................................................................................................................... 33
Table 23: Related Bit / Register in Chapter 3.11 ......................................................................................................................................................... 35
Table 24: Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 36
Table 25: Outputs on OUT1 & OUT2 if Derived from T0/T4 DPLL Outputs ................................................................................................................ 36
Table 26: Outputs on OUT1 & OUT2 if Derived from T0/T4 APLL .............................................................................................................................. 37
Table 27: Frame Sync Input Signal Selection .............................................................................................................................................................. 38
Table 28: Synchronization Control ............................................................................................................................................................................... 38
Table 29: Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 39
Table 30: Related Bit / Register in Chapter 3.14 ......................................................................................................................................................... 40
Table 31: Read Timing Characteristics in Serial Mode ................................................................................................................................................ 44
Table 32: Write Timing Characteristics in Serial Mode ................................................................................................................................................ 44
Table 33: JTAG Timing Characteristics ....................................................................................................................................................................... 45
Table 34: Register List and Map .................................................................................................................................................................................. 46
Table 35: Power Consumption and Maximum Junction Temperature ....................................................................................................................... 111
Table 36: Thermal Data ............................................................................................................................................................................................. 111
Table 37: Absolute Maximum Rating ......................................................................................................................................................................... 112
Table 38: Recommended Operation Conditions ........................................................................................................................................................ 112
Table 39: CMOS Input Port Electrical Characteristics ............................................................................................................................................... 113
Table 40: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics ................................................................................................ 113
Table 41: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ........................................................................................... 113
Table 42: CMOS Output Port Electrical Characteristics ............................................................................................................................................ 113
Table 43: PECL Input / Output Port Electrical Characteristics ................................................................................................................................... 115
Table 44: LVDS Input / Output Port Electrical Characteristics ................................................................................................................................... 116
Table 45: Output Clock Jitter Generation .................................................................................................................................................................. 117
Table 46: Output Clock Phase Noise ......................................................................................................................................................................... 118
Table 47: Input Jitter Tolerance (155.52 MHz) .......................................................................................................................................................... 118
Table 48: Input Jitter Tolerance (1.544 MHz) ............................................................................................................................................................ 118
List of Tables
6
December 3, 2008