IDT82V3255TFG8 IDT, Integrated Device Technology Inc, IDT82V3255TFG8 Datasheet - Page 104

• Manufacturer Part Number: IDT82V3255TFG8
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG8

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG8

OUT1_FREQ_CNFG - Output Clock 1 Frequency Configuration
OUT1_INV_CNFG - Output Clock 1 Invert Configuration
Programming Information
IDT82V3255
Address:71H
Type: Read / Write
Default Value: 00001000
Address:72H
Type: Read / Write
Default Value: XXXXXX0X
OUT1_PATH_S
7 - 4
3 - 0
7 - 2
Bit
Bit
1
0
EL3
7
7
-
OUT1_PATH_SEL[3:0]
OUT1_DIVIDER[3:0]
OUT1_INV
OUT1_PATH_S
Name
Name
-
-
EL2
6
6
-
Reserved.
This bit determines whether the output on OUT1 is inverted.
0: Not inverted. (default)
1: Inverted.
Reserved.
These bits select an input to OUT1.
0000 ~ 0011: The output of T0 APLL. (default: 0000)
0100: The output of T0 DPLL 77.76 MHz path.
0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T0 DPLL 16E1/16T1 path.
0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
1000 ~ 1011: The output of T4 APLL.
1100: The output of T4 DPLL 77.76 MHz path.
1101: The output of T4 DPLL 12E1/24T1/E3/T3 path.
1110: The output of T4 DPLL 16E1/16T1 path.
1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path.
These bits select a division factor of the divider for OUT1.
The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output
(selected by the OUT1_PATH_SEL[3:0] bits (b7~4, 71H)). If the signal is derived from one of the T0/T4 DPLL outputs,
please refer to
Table 26
OUT1_PATH_S
EL1
5
5
-
for the division factor selection.
Table 25
OUT1_PATH_S
for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to
EL0
4
4
-
104
OUT1_DIVIDER
3
3
3
-
Description
Description
OUT1_DIVIDER
2
2
2
-
OUT1_DIVIDER
OUT1_INV
1
1
1
December 3, 2008
OUT1_DIVIDER
0
0
0
-
WAN PLL