IDT82V3255TFG8 IDT, Integrated Device Technology Inc, IDT82V3255TFG8 Datasheet - Page 51

• Manufacturer Part Number: IDT82V3255TFG8
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG8

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG8

Table 34: Register List and Map (Continued)
6.2
6.2.1
ID[7:0] - Device ID 1
ID[15:8] - Device ID 2
Programming Information
IDT82V3255
Address
Address: 00H
Type: Read
Default Value: 10001000
Address: 01H
Type: Read
Default Value: 00010001
(Hex)
7A
7B
7C
7D
73
74
78
7 - 0
7 - 0
Bit
Bit
ID15
ID7
OUT2_INV_CNFG - Output Clock 2
Invert Configuration
FR_MFR_SYNC_CNFG - Frame Sync
& Multiframe Sync Output Configura-
tion
PHASE_MON_PBO_CNFG - Phase
Transient Monitor & PBO Configura-
tion
PHASE_OFFSET[7:0]_CNFG - Phase
Offset Configuration 1
PHASE_OFFSET[9:8]_CNFG - Phase
Offset Configuration 2
SYNC_MONITOR_CNFG - Sync Mon-
itor Configuration
SYNC_PHASE_CNFG - Sync Phase
Configuration
7
7
REGISTER DESCRIPTION
GLOBAL CONTROL REGISTERS
Register Name
ID[15:8]
ID[7:0]
Name
Name
ID14
ID6
6
6
Refer to the description of the ID[15:8] bits (b7~0, 01H).
The value in the ID[15:0] bits are pre-set, representing the identification number for the IDT82V3255.
ID13
ID5
IN_2K_4K_
_WINDOW
IN_NOISE
PH_OFFS
SYNC_BY
5
5
8K_INV
ET_EN
PASS
Bit 7
-
-
Synchronization Configuration Registers
PBO & Phase Offset Control Registers
8K_EN
Bit 6
-
-
-
-
ID12
ID4
SYNC_MON_LIMT[2:0]
4
4
PH_MON_
2K_EN
Bit 5
SYNC_PH3[1:0]
EN
51
-
-
2K_8K_PU
PH_MON_
ID11
L_POSITI
ID3
PBO_EN
3
3
Bit 4
PH_OFFSET[7:0]
ON
Description
Description
-
-
8K_INV
Bit 3
SYNC_PH2[1:0]
-
-
-
ID10
ID2
2
2
PH_TR_MON_LIMT[3:0]
OUT2_INV
8K_PUL
Bit 2
-
-
2K_INV
ID1
ID9
1
1
Bit 1
PH_OFFSET[9:8]
SYNC_PH1[1:0]
-
-
December 3, 2008
2K_PUL
Bit 0
-
-
ID0
ID8
0
0
WAN PLL
Reference
P 105
P 106
P 107
P 108
P 109
P 107
P 110
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