IDT82V3255TFG8 IDT, Integrated Device Technology Inc, IDT82V3255TFG8 Datasheet - Page 27

• Manufacturer Part Number: IDT82V3255TFG8
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG8

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG8

Table 15: Related Bit / Register in Chapter 3.8
3.8.2.2
when another qualified input clock with a higher priority than the current
selected input clock is available. In this case, the selected input clock is
switched and a qualified input clock with the highest priority is selected
only when the T0 selected input clock is disqualified. If more than one
qualified input clock is available and has the same priority, the input
clock with the smallest ‘n’ is selected. See
each input clock.
3.8.3
CURRENTLY_SELECTED_INPUT[3:0] bits. Note if the T4 selected
input clock is a T0 DPLL output, it can not be indicated by these bits.
Functional Description
Note: * The setting in the 27, 28, 2A, 4E and 4F registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
IDT82V3255
INn_CMOS_NO_ACTIVITY_ALARM (n = 1, 2 or 3)
INn_CMOS_FREQ_HARD_ALARM (n = 1, 2 or 3)
In Non-Revertive switch, the T0 selected input clock is not switched
The
INn_CMOS
INn_CMOS
INn_CMOS
INn_DIFF_NO_ACTIVITY_ALARM (n = 1 or 2)
INn_DIFF_FREQ_HARD_ALARM (n = 1 or 2)
INn_CMOS_PH_LOCK_ALARM (
INn_CMOS_SEL_PRIORITY[3:0] (n = 1, 2 or 3)
INn_DIFF_SEL_PRIORITY[3:0] (n = 1 or 2)
INn_DIFF_PH_LOCK_ALARM (n = 1 or 2)
HIGHEST_PRIORITY_VALIDATED[3:0]
CURRENTLY_SELECTED_INPUT[3:0]
SECOND_PRIORITY_VALIDATED[3:0]
THIRD_PRIORITY_VALIDATED[3:0]
selected
Non-Revertive Switch (T0 only)
SELECTED / QUALIFIED INPUT CLOCKS INDICATION
1
2
3
T0_MAIN_REF_FAILED
T0_MAIN_REF_FAILED
(n = 1, 2 or 3) / INn_DIFF
(n = 1, 2 or 3) / INn_DIFF
(n = 1, 2 or 3) / INn_DIFF
LOS_FLAG_TO_TDO
IN_NOISE_WINDOW
REVERTIVE_MODE
ULTR_FAST_SW
INPUT_TO_T4
INPUT_TO_T4
T0_FOR_T4
T4_T0_SEL
input
Bit
clock
1
2
n = 1, 2 or 3
1
2
1
2
3
(n = 1 or 2)
(n = 1 or 2)
(n = 1 or 2)
Table 9
is
)
indicated
for the ‘n’ assigned to
IN1_IN2_CMOS_SEL_PRIORITY_CNFG, IN3_CMOS_SEL_PRIORITY_CNFG
INTERRUPTS1_ENABLE_CNFG, INTERRUPTS2_ENABLE_CNFG
by
the
INPUT_VALID1_STS, INPUT_VALID2_STS
INTERRUPTS1_STS, INTERRUPTS2_STS
27
IN1_IN2_CMOS_STS, IN3_CMOS_STS
IN1_IN2_DIFF_SEL_PRIORITY_CNFG
cated by HIGHEST_PRIORITY_VALIDATED[3:0] bits, the SECOND_
PRIORITY_VALIDATED[3:0]
_VALIDATED[3:0] bits respectively. If more than one input clock has the
same priority, the input clock with the smallest ‘n’ is indicated by the
HIGHEST_PRIORITY_VALIDATED[3:0] bits. See
assigned to the input clock.
switch
CURRENTLY_SELECTED_INPUT[3:0] bits is the same as the one indi-
cated by the HIGHEST_PRIORITY_VALIDATED[3:0] bits; otherwise,
they are not the same.
INPUT_TO_T4
rupt will be generated.
INTERRUPTS2_ENABLE_CNFG
INTERRUPTS3_ENABLE_CNFG
The qualified input clocks with the three highest priorities are indi-
When the device is configured in Automatic selection and Revertive
When all the input clocks for T4 path changes to be unqualified, the
PHASE_MON_PBO_CNFG
PRIORITY_TABLE1_STS
PRIORITY_TABLE2_STS
T4_T0_REG_SEL_CNFG
T4_INPUT_SEL_CNFG
MON_SW_PBO_CNFG
INPUT_MODE_CNFG
INTERRUPTS2_STS
INTERRUPTS3_STS
IN1_IN2_DIFF_STS
is
Register
enabled,
1
bit will be set. If the INPUT_TO_T4
the
bits
input
and
clock
the
indicated
December 3, 2008
Table 9
THIRD_PRIORITY
2
bit is ‘1’, an inter-
Address (Hex)
27 *, 2A *
4A, 4B
0D, 0E
10, 11
44, 47
4E *
28 *
4F *
WAN PLL
for the ‘n’
0B
51
45
78
0E
0F
12
09
07
11
by
the