IDT5V49EE702NDGI8 IDT, Integrated Device Technology Inc, IDT5V49EE702NDGI8 Datasheet - Page 28

• Manufacturer Part Number: IDT5V49EE702NDGI8
• Description: IC PLL CLK GEN 200MHZ 28VQFN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generator, Multiplexerr

Specifications of IDT5V49EE702NDGI8

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL, Crystal
• Output: HCSL, LVCMOS, LVDS, LVPECL, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:7
• Differential - Input:output: No/Yes
• Frequency - Max: 500MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: IDT5V49EE702DLGI8; IDT5V49EE702DLGI8

IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
Addr
0x7C
0x7D
0x8C
0x8D
0x9C
0x9D
0x77
0x78
0x79
0x7A
0x7B
0x7E
0x7F
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8E
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9E
0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
0xA6
IDT5V49EE702
EEPROM PROGRAMMABLE CLOCK GENERATOR
Register
Default
Value
Hex
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
FF
FF
FF
FF
FF
FF
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
PM1_CFG0
PM1_CFG1
PM1_CFG2
PM1_CFG3
PM1_CFG4
PM1_CFG5
PM2_CFG4
PM2_CFG5
PM2_CFG0
PM2_CFG1
PM2_CFG2
PM2_CFG3
PM3_CFG0
PM3_CFG1
PM3_CFG2
PM3_CFG3
PM3_CFG4
PM3_CFG5
PM4_CFG4
PM4_CFG5
PM4_CFG0
PM4_CFG1
PM4_CFG2
PM4_CFG3
PM5_CFG0
PM5_CFG1
PM5_CFG2
PM5_CFG3
PM5_CFG4
PM5_CFG5
PM6_CFG4
7
OEM3[1:0]
OEM5[1:0]
6
5
SLEW2[1:0]
SLEW3[1:0]
SLEW5[1:0]
SLEW6[1:0]
SSVCO[15:8]_CFG0
SSVCO[15:8]_CFG1
SSVCO[15:8]_CFG2
SSVCO[15:8]_CFG3
SSVCO[15:8]_CFG4
SSVCO[15:8]_CFG5
4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit #
Q1[6:0]_CFG0
Q1[6:0]_CFG1
Q1[6:0]_CFG2
Q1[6:0]_CFG3
Q1[6:0]_CFG4
Q1[6:0]_CFG5
Q2[6:0]_CFG4
Q2[6:0]_CFG5
Q2[6:0]_CFG0
Q2[6:0]_CFG1
Q2[6:0]_CFG2
Q2[6:0]_CFG3
Q3[6:0]_CFG0
Q3[6:0]_CFG1
Q3[6:0]_CFG2
Q3[6:0]_CFG3
Q3[6:0]_CFG4
Q3[6:0]_CFG5
Q4[6:0]_CFG4
Q4[6:0]_CFG5
Q4[6:0]_CFG0
Q4[6:0]_CFG1
Q4[6:0]_CFG2
Q4[6:0]_CFG3
Q5[6:0]_CFG0
Q5[6:0]_CFG1
Q5[6:0]_CFG2
Q5[6:0]_CFG3
Q5[6:0]_CFG4
Q5[6:0]_CFG5
Q6[6:0]_CFG4
28
3
INV3[1:0]
INV5[1:0]
2
CMEN3
CMEN5
1
LVL3[1:0]
LVL5[1:0]
CMEN1
CMEN4
0
IDT5V49EE702
CLOCK SYNTHESIZER
CMEN# - common mode enable
Set to 1 for LVDS
Set to 0 for LVTTL, LVPECL,
HCSL
OEM3 controls OUT3 and OUT6
OEM5 controls OUT5 and
OUT5b
PLL3 Spread Spectrum
Feedback Counter
Reserved
Reserved
Output Divides
for Q<>111111,
PM=0 - Divide by 2
PM=1, (Q+2)*2
for Q=1111111
PM=0, disable the output divider
PM=1, bypass the output divide,
(divide by 1)
Description
REV F 022310