IDT5V49EE702NDGI8 IDT, Integrated Device Technology Inc, IDT5V49EE702NDGI8 Datasheet - Page 8

• Manufacturer Part Number: IDT5V49EE702NDGI8
• Description: IC PLL CLK GEN 200MHZ 28VQFN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generator, Multiplexerr

Specifications of IDT5V49EE702NDGI8

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL, Crystal
• Output: HCSL, LVCMOS, LVDS, LVPECL, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:7
• Differential - Input:output: No/Yes
• Frequency - Max: 500MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: IDT5V49EE702DLGI8; IDT5V49EE702DLGI8

values range from 1 to 6. Values of 0 and 7 should not be
used.
SS_OFFSET[5:0]
These bits are used to program the fractional offset with
respect to the nominal M integer value. For center spread,
the SS_OFFSET is set to '0' so that the spread spectrum
waveform is centered about the nominal M (Mnom) value.
For down spread, the SS_OFFSET > '0' such the spread
spectrum waveform is centered about the (Mideal -1
+SS_Offset) value. The downspread percentage can be
thought of in terms of center spread. For example, a
downspread of -1% can also be considered as a center
spread of ±0.5% but with Mnom shifted down by one and
offset. The SS_OFFSET has integer values ranging from 0
to 63.
SD[3:0]
These bits are used to shape the profile of the spread
spectrum waveform. These are delta-encoded samples of
the waveform. There are twelve sets of SD samples. The
NSSC bits determine how many of these samples are used
for the waveform. The sum of these delta-encoded samples
(sigma delta- encoded samples) determine the amount of
spread and should not exceed (63 - SS_OFFSET). The
maximum spread is inversely proportional to the nominal M
integer value.
DITH
This bit is used for dithering the sigma-delta-encoded
samples. This will randomize the least-significant bit of the
input to the spread spectrum modulator. Set the bit to '1' to
enable dithering.
X2
This bit will double the total value of the
sigma-delta-encoded-samples which will increase the
amplitude of the spread spectrum waveform by a factor of
two. When X2 is '0', the amplitude remains nominal but if set
to '1', the amplitude is increased by x2. The following
equations govern how the spread spectrum is set:
T
N
SD[3:0]
where S
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
SSC
SSC
IDT5V49EE702
EEPROM PROGRAMMABLE CLOCK GENERATOR
= TSSC[3:0] + 2 (Eq. 2)
= NSSC[2:0] * 2 (Eq. 3)
K
J
= S
is the unencoded sample out of a possible 12 and
J+1
(unencoded) - S
J
(unencoded) (Eq. 4)
8
SD
Amplitude = ((2*N[11:0] + A[3:0] + 1) * Spread% / 100) /2
(Eq. 5)
if 1 < Amplitude < 2, then set X2 bit to '1'.
Modulation frequency:
F
F
F
Spread:
Σ∆ = SD
the number of samples used depends on the N
Σ∆< 63 - SS_OFFSET
±Spread% = (Σ∆ * 100)/(64 * (2*N[11:0] + A[3:0] + 1) (Eq. 9)
±Max Spread% / 100 = 1 / M
PFD
VCO
SSC
K
is the delta-encoded sample out of a possible 12.
= F
= F
= F
IN
PFD
PFD
0
+ SD
/ D (Eq. 6)
/ (4 * Nssc * Tssc) (Eq. 8)
* M
1
NOM
+ SD
(Eq. 7)
2
+ … + SD
NOM
11
IDT5V49EE702
or 2 / M
CLOCK SYNTHESIZER
NOM
(X2=1)
SSC
REV F 022310
value