MPC9600AE IDT, Integrated Device Technology Inc, MPC9600AE Datasheet - Page 6

• Manufacturer Part Number: MPC9600AE
• Description: IC PLL CLK DRIVER LV 48-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MPC9600AE

• Pll: Yes with Bypass
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:22
• Differential - Input:output: Yes/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Frequency-max: 200MHz
• Number Of Elements: 1
• Supply Current: 5mA
• Pll Input Freq (min): 16.67MHz
• Pll Input Freq (max): 50MHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TQFP
• Output Frequency Range: 50 to 200MHz
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER
MPC9600
LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER
Table 7. AC Characteristics – 48 LQFP (V
1. AC characteristics are applicable over the entire ambient temperature and supply voltage range and are production tested. AC
2. V
3. Cycle-to-cycle and period jitter depends on output divider configuration.
4. See
Symbol
t
V
t
t
t
JIT(PER)
PLZ, HZ
PZL, ZH
JIT(CC)
t
characteristics apply for parallel output termination of 50 Ω to V
and the input swing lies within the V
f
t
CMR
f
f
t
JIT(∅)
refDC
LOCK
V
t
sk(o)
t
BW
VCO
MAX
t
DC
f
CMR
r
r
(∅)
ref
, t
, t
PP
f
f
(2)
Applications Information
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
Input Frequency
VCO Frequency
Maximum Output Frequency
Reference Input Duty Cycle
Peak-to-Peak Input Voltage
Common Mode Range
CCLK Input Rise/Fall Time
Propagation Delay (static phase offset)
Output-to-Output Skew
Output Duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
PLL Closed Loop Bandwidth
Cycle-to-Cycle Jitter
Period Jitter
I/O Phase Jitter (1 σ)
Maximum PLL Lock Time
(3)
section for max I/O phase jitter versus frequency.
Characteristics
(3)
PCLK, PCLK (V
PCLK, PCLK (V
Static test mode (V
PP
All outputs in ÷ 2 configuration
All outputs in ÷ 4 configuration
All outputs in ÷ 2 configuration
All outputs in ÷ 4 configuration
÷ 12 feedback (FSEL_FB = 1)
all outputs, multiple frequency
÷ 8 feedback (FSEL_FB = 0)
÷ 12 feedback (FSEL_FB=1)
all outputs, single frequency
÷ 8 feedback (FSEL_FB=0)
(AC) specification. Violation of V
÷ 2 outputs (FSELx = 0)
÷ 4 outputs (FSELx = 1)
within QAx output bank
CC
PECL_CLK to FB_IN
within QBx outputs
within QCx outputs
= 3.3 V ± 5% or V
CC
CC
CCLK to FB_IN
= 3.3 V ± 5%)
= 2.5 V ± 5%)
PCLK, PCLK
CCA
V
V
CC
CC
= GND)
= 3.3 V
= 2.5 V
TT
.
6
CC
CMR
= 2.5 V ± 5%, T
16.67
Min
200
100
500
–60
+30
1.2
1.2
0.1
25
50
25
45
0
or V
PP
impacts static phase offset t
0.6 – 4.0
1.0 – 10
+130
Typ
+40
70
70
30
40
30
50
40
40
25
20
A
= –40°C to +85°C)
V
V
CC
CC
+140
+230
1000
Max
17
15
500
400
200
100
150
150
125
130
180
100
1.0
1.0
5.0
50
33
75
75
75
55
10
10
70
–0.8
–0.6
(4)
(3)
MPC9600 REV. 5 NOVEMBER 10, 2008
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
mV
ms
(∅).
ns
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ps
ps
ps
ps
ps
ps
%
%
V
V
(1)
PLL locked
PLL locked
V
PLL locked
PLL locked
LVPECL
LVPECL
LVPECL
see
PLL locked
PLL locked
Measured at
coincident rising
edge
see
–3 dB point of PLL
transfer
characteristic
Refer to
application
section for other
configurations
Refer to
application
section for other
configurations
RMS value at
f
VCO
CCA
Condition
Figure 11
Figure 11
= 400 MHz
= GND
CMR
range