MPC9600AE IDT, Integrated Device Technology Inc, MPC9600AE Datasheet - Page 10

• Manufacturer Part Number: MPC9600AE
• Description: IC PLL CLK DRIVER LV 48-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MPC9600AE

• Pll: Yes with Bypass
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:22
• Differential - Input:output: Yes/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Frequency-max: 200MHz
• Number Of Elements: 1
• Supply Current: 5mA
• Pll Input Freq (min): 16.67MHz
• Pll Input Freq (max): 50MHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TQFP
• Output Frequency Range: 50 to 200MHz
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

specified. I/O jitter numbers for other confidence factors (CF) can
be derived from
and can be used to fine-tune the effective delay through each
device. In the following example calculation a
I/O jitter confidence factor of 99.7% (± 3σ) is assumed, resulting
in a worst case timing uncertainty from input to any output of –
261 ps to 341 ps relative to CCLK (V
MHz):
t
t
the AC characteristic table for V
is frequency dependant with a maximum at the lowest VCO
frequency (200 MHz for the MPC9600). Applications using a
higher VCO frequency exhibit less I/O jitter than the AC
characteristic limit. The I/O jitter characteristics in
used to derive a smaller
I/O jitter number at the specific VCO frequency, resulting in tighter
timing limits in zero-delay mode and for part-to-part skew t
Driving Transmission Lines
signals in a terminated transmission line environment. To provide
the optimum flexibility to the user the output drivers were designed
to exhibit the lowest impedance possible. With an output
impedance of less than 20 Ω the drivers can drive either parallel
IDT™ / ICS™ 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER
SK(PP)
SK(PP)
MPC9600
LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER
Table 11. Confidence Factor CF
Due to the statistical nature of I/O jitter a RMS value (1 σ) is
The feedback trace delay is determined by the board layout
Above equation uses the maximum I/O jitter number shown in
The MPC9600 clock driver was designed to drive high speed
18
16
14
12
10
± 1σ
± 2σ
± 3σ
± 4σ
± 5σ
± 6σ
8
6
4
2
0
CF
200
= [–60 ps...140 ps] + [–150 ps...150 ps] +
= [–261 ps...341 ps] + t
Figure 7. I/O Jitter versus VCO Frequency for
[(17 ps @ –3)...(17 ps @ 3)] + t
Maximum I/O Jitter versus Frequency
220 240
V
CC
Probability of Clock Edge Within the Distribution
Table
= 2.5 V
V
CC
260 280
11.
= 2.5 V and V
V
CC
= 3.3 V
300 320
PD, LINE(FB)
CC
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
= 3.3 V (17 ps RMS). I/O jitter
CC
CC
VCO FREQUENCY (MHz)
= 3.3 V and f
= 3.3 V
340
PD, LINE(FB)
360 380
Figure 7
VCO
400
= 200
can be
SK(PP)
.
10
or series terminated transmission lines. For more information on
transmission lines the reader is referred to Freescale
Semiconductor application note AN1091. In most high
performance clock networks point-to-point distribution of signals
is the method of choice. In a point-to-point scheme either series
terminated or parallel terminated transmission lines can be used.
The parallel technique terminates the signal at the end of the line
with a 50 Ω resistance to V
only a single terminated line can be driven by each output of the
MPC9600 clock driver. For the series terminated case however
there is no DC current draw, thus the outputs can drive multiple
series terminated lines.
single series terminated line versus two series terminated lines in
parallel. When taken to its extreme the fanout of the MPC9600
clock driver is effectively doubled due to its capability to drive
multiple lines.
an output driving a single line versus two lines. In both cases the
drive capability of the MPC9600 output buffer is more than
sufficient to drive 50 Ω transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta of
only 43 ps exists between the two differently loaded outputs. This
suggests that the dual line driving need not be used exclusively to
maintain the tight output-to-output skew of the MPC9600. The
output waveform in
step is caused by the impedance mismatch seen looking into the
driver. The parallel combination of the 36 Ω series resistor plus the
output impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two lines
will equal:
This technique draws a fairly high level of DC current and thus
IN
IN
The waveform plots in
V
Z
R
R
V
0
L
L
S
0
Figure 8. Single versus Dual Transmission Lines
= V
= 50 Ω || 50 Ω
= 36 Ω || 36 Ω
= 14 Ω
= 3.0 (25 ÷ (18 + 17 + 25)
= 1.31 V
MPC9600
MPC9600
Output
Output
14 Ω
Buffer
Buffer
14 Ω
S
(Z
0
÷ (R
Figure 9
S
Figure 8
+ R
R
R
R
Figure 9
S
S
S
= 36 Ω
= 36 Ω
= 36 Ω
CC
0
MPC9600 REV. 5 NOVEMBER 10, 2008
shows a step in the waveform, this
+ Z
÷2.
0
illustrates an output driving a
))
shows the simulation results of
Z
Z
Z
O
O
O
= 50 Ω
= 50 Ω
= 50 Ω
OutA
OutB0
OutB1