ICS87004AGLF IDT, Integrated Device Technology Inc, ICS87004AGLF Datasheet - Page 7

• Manufacturer Part Number: ICS87004AGLF
• Description: IC CLK GENERATOR ZD 1:4 24-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr

Specifications of ICS87004AGLF

• Pll: Yes with Bypass
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVCMOS, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: Yes/No
• Frequency - Max: 250MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Frequency-max: 250MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1192; 800-1192-5; 800-1192; 87004AGLF

ICS87004 Data Sheet
AC Electrical Characteristics
Table 5A. AC Characteristics, V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the output at V
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and
the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. AC Characteristics, V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the output at V
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and
the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS87004AG REVISION C DECEMBER 1, 2009
Symbol
f
t
t(Ø)
tsk(o)
tjit(cc)
t
t
odc
Symbol
f
t
t(Ø)
tsk(o)
tjit(cc)
t
t
odc
MAX
PD
L
R
MAX
PD
L
R
/ t
/ t
F
F
Parameter
Output Frequency
Propagation Delay;
NOTE 1
Static Phase Offset;
NOTE 2, 4
Output Skew;
NOTE 3, 4
Cycle-to-Cycle Jitter; NOTE 4
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
Parameter
Output Frequency
Propagation Delay;
NOTE 1
Static Phase Offset;
NOTE 2, 4
Output Skew;
NOTE 3, 4
Cycle-to-Cycle Jitter; NOTE 4
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
CLK0, nCLK0
CLK1, nCLK1
CLK0, nCLK0
CLK1, nCLK1
CLK0, nCLK0
CLK1, nCLK1
CLK0, nCLK0
CLK1, nCLK1
CLK0, nCLK0
CLK1, nCLK1
CLK0, nCLK0
CLK1, nCLK1
DD
DD
= V
= V
DDO
DDO
= 3.3V ± 5%, T
= 2.5V ± 5%, T
PLL_SEL = 0V, f ≤ 250MHz,
PLL_SEL = 0V, f ≤ 250MHz,
f
f
REF
REF
PLL_SEL = 3.3V,
PLL_SEL = 2.5V,
Test Conditions
Test Conditions
PLL_SEL = 0V
PLL_SEL = 0V
f
f
≤ 167MHz, Qx ÷ 1
≤ 167MHz, Qx ÷ 1
OUT
OUT
20% to 80%
20% to 80%
A
A
Qx ÷ 2
Qx ÷ 2
= 0°C to 70°C
= 0°C to 70°C
> 40MHz
> 40MHz
7
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
DDO
DDO
/2.
/2.
Minimum
Minimum
15.625
15.625
-190
-175
-290
400
400
-75
5.3
40
44
5
Typical
Typical
©2009 Integrated Device Technology, Inc.
-115
-65
-25
50
40
30
50
40
35
50
DDO
DDO
Maximum
Maximum
250
175
175
800
250
125
125
700
6.2
6.9
/2.
/2.
50
45
60
45
45
56
1
1
Units
Units
MHz
MHz
ms
ms
ns
ps
ps
ps
ps
ps
ns
ps
ps
ps
ps
ps
%
%