ICS87004AGLF IDT, Integrated Device Technology Inc, ICS87004AGLF Datasheet

IC CLK GENERATOR ZD 1:4 24-TSSOP

ICS87004AGLF

Manufacturer Part Number
ICS87004AGLF
Description
IC CLK GENERATOR ZD 1:4 24-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr
Datasheet

Specifications of ICS87004AGLF

Pll
Yes with Bypass
Input
HCSL, LVDS, LVHSTL, LVPECL, SSTL
Output
LVCMOS, LVTTL
Number Of Circuits
1
Ratio - Input:output
2:4
Differential - Input:output
Yes/No
Frequency - Max
250MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
2.375 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Frequency-max
250MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-1192
800-1192-5
800-1192
87004AGLF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS87004AGLF
Manufacturer:
IDT Integrated Device Technolo
Quantity:
135
Part Number:
ICS87004AGLF
Manufacturer:
IDT
Quantity:
91
Block Diagram
CLK_SEL
General Description
pairs can accept most standard differential input levels. Internal bias
on the nCLK0 and nCLK1 inputs allows the CLK0 and CLK1 inputs
to accept LVCMOS/LVTTL. The ICS87004 has a fully integrated PLL
and can be configured as zero delay buffer, multiplier or divider and
has an input and output frequency range of 15.625MHz to 250MHz.
The reference divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external
feedback allows the device to achieve “zero delay” between the input
clock and the output clocks. The PLL_SEL pin can be used to
bypass the PLL for system test and debug purposes. In bypass
mode, the reference clock is routed around the PLL and into the
internal output dividers.
PLL_SEL
ICS87004AG REVISION C DECEMBER 1, 2009
HiPerClockS™
ICS
nCLK0
nCLK1
FB_IN
CLK0
CLK1
SEL0
SEL2
SEL3
SEL1
MR
Pullup
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
The ICS87004 is a highly versatile 1:4 Differential-
to-LVCMOS/LVTTL Clock Generator and a member of
the HiPerClockS® family of High Performance Clock
Solutions from IDT. The ICS87004 has two selectable
clock inputs. The CLK0, nCLK0 and CLK1, nCLK1
0
1
1:4, Differential-to-LVCMOS/LVTTL
Zero Delay Clock Generator
÷2, ÷4, ÷8, ÷16
÷32, ÷64, ÷128
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
PLL
0
1
Q0
Q1
Q2
Q3
1
Features
Four LVCMOS/LVTTL outputs, 7
Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs
CLKx/nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL
levels on CLK0 and CLK1 inputs
Output frequency range: 15.625MHz to 250MHz
Input frequency range: 15.625MHz to 250MHz
VCO range: 250MHz to 500MHz
External feedback for “zero delay” clock regeneration with
configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Fully integrated PLL
Cycle-to-cycle jitter: 45ps (maximum)
Output skew: 50ps (maximum)
Static phase offset: 50ps ± 125ps (3.3V ± 5%), CLK0/nCLK0
Full 3.3V or 2.5V output operating supply
5V tolerant inputs
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
7.8mm x 4.4mm x 0.925mm package body
CLK_SEL
nCLK0
SEL0
SEL1
SEL2
SEL3
CLK0
V
GND
GND
V
DDO
24-Lead TSSOP
Q0
DD
G Package
©2009 Integrated Device Technology, Inc.
ICS87004
Top View
1
2
3
4
5
6
7
8
9
10
11
12
typical output impedance
24
23
22
21
20
19
18
17
16
15
14
13
Q1
V
Q2
GND
Q3
V
MR
PLL_SEL
CLK1
nCLK1
DDO
DDO
DATA SHEET
ICS87004

Related parts for ICS87004AGLF

ICS87004AGLF Summary of contents

Page 1

Differential-to-LVCMOS/LVTTL Zero Delay Clock Generator General Description The ICS87004 is a highly versatile 1:4 Differential- ICS to-LVCMOS/LVTTL Clock Generator and a member of the HiPerClockS® family of High Performance Clock HiPerClockS™ Solutions from IDT. The ICS87004 has two selectable ...

Page 2

ICS87004 Data Sheet Table 1. Pin Descriptions Number Name 1, 12, 21 GND Power 2, 20, Q0, Q3, Output 22 Power DDO 4, 5, SEL0, SEL1, Input 6, 7 SEL2, SEL3 8 CLK_SEL ...

Page 3

ICS87004 Data Sheet Function Tables Table 3A. PLL Enable Function Table SEL3 SEL2 SEL1 ...

Page 4

ICS87004 Data Sheet Table 3B. PLL Bypass Function Table Inputs SEL3 SEL2 SEL1 ...

Page 5

ICS87004 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those ...

Page 6

ICS87004 Data Sheet Table 4C. LVCMOS/LVTTL DC Characteristics, V Symbol Parameter V Input High Voltage IH V Input Low Voltage IL SEL[0:3], MR, FB_IN, CLK_SEL I Input High Current IH PLL_SEL SEL[0:3], MR, FB_IN, CLK_SEL I Input Low Current IL ...

Page 7

ICS87004 Data Sheet AC Electrical Characteristics Table 5A. AC Characteristics, V Symbol Parameter f Output Frequency MAX Propagation Delay; CLK0, nCLK0 t PD NOTE 1 CLK1, nCLK1 CLK0, nCLK0 Static Phase Offset; t(Ø) NOTE 2, 4 CLK1, nCLK1 Output Skew; ...

Page 8

ICS87004 Data Sheet Parameter Measurement Information 1.65V±5% V DD, V DDA, V DDO LVCMOS GND -1.65V±5% 3.3V Output Load AC Test Circuit V DD nCLK[0:1] V Cross Points PP CLK[0:1] GND Differential Input Level V DDO 2 Q[0:3] ➤ ➤ ...

Page 9

ICS87004 Data Sheet Parameter Measurement Information, continued 80% 20% Q[0: Output Rise/Fall Time V DDO 2 Q[0: PERIOD t PW odc = t PERIOD Output Duty Cycle/Pulse Width/Period ICS87004AG REVISION C DECEMBER 1, 2009 1:4, ...

Page 10

ICS87004 Data Sheet Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS87004 provides separate power ...

Page 11

ICS87004 Data Sheet Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING and V input requirements. Figures show interface CMR examples for the HiPerClockS CLK/nCLK input ...

Page 12

ICS87004 Data Sheet Reliability Information θ Table 6. vs. Air Flow Table for a 24 Lead TSSOP JA Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS87004 is: 2578 Package Outline and ...

Page 13

... ICS87004AGLF 87004AGLFT ICS87004AGLF NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use ...

Page 14

ICS87004 Data Sheet Revision History Sheet Rev Table Page Ordering Information Table - added Lead-Free marking Ordering Information Table - corrected Lead-Free part number. Added Lead-Free note. T5A 6 3.3V AC Characteristics Table - ...

Page 15

ICS87004 Data Sheet 6024 Silver Creek Valley Road Sales 800-345-7015 (inside USA) San Jose, California 95138 +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications ...

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