ICS87004AGLF IDT, Integrated Device Technology Inc, ICS87004AGLF Datasheet - Page 11

• Manufacturer Part Number: ICS87004AGLF
• Description: IC CLK GENERATOR ZD 1:4 24-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr

Specifications of ICS87004AGLF

• Pll: Yes with Bypass
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVCMOS, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: Yes/No
• Frequency - Max: 250MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Frequency-max: 250MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1192; 800-1192-5; 800-1192; 87004AGLF

ICS87004 Data Sheet
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both V
and V
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
Figure 3A. HiPerClockS CLK/nCLK Input
Figure 3C. HiPerClockS CLK/nCLK Input
Figure 3E. HiPerClockS CLK/nCLK Input
ICS87004AG REVISION C DECEMBER 1, 2009
CMR
2.5V
1.8V
3.3V
HCSL
LVPECL
*Optional – R3 and R4 can be 0Ω
input requirements. Figures 3A to 3F show interface
LVHSTL
IDT
HiPerClockS
LVHSTL Driver
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Driven by a 3.3V LVPECL Driver
Driven by a 3.3V HCSL Driver
*R3
*R4
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
33
33
Zo = 50Ω
Zo = 50Ω
SWING
R3
125
R1
50
3.3V
R1
84
R1
50
and V
R4
125
R2
50
R2
84
R2
50
OH
CLK
nCLK
CLK
nCLK
must meet the V
CLK
nCLK
3.3V
3.3V
3.3V
Differential
Input
Differential
Input
Differential
Input
PP
11
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
Figure 3B. HiPerClockS CLK/nCLK Input
Figure 3D. HiPerClockS CLK/nCLK Input
Figure 3F. HiPerClockS CLK/nCLK Input
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
2.5V
3.3V
3.3V
SSTL
LVDS
LVPECL
Driven by a 3.3V LVPECL Driver
Driven by a 3.3V LVDS Driver
Driven by a 2.5V SSTL Driver
Zo = 60Ω
Zo = 60Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
©2009 Integrated Device Technology, Inc.
R3
120
2.5V
R1
120
R1
50
R2
50
R4
120
R2
120
R2
50
R1
100
CLK
nCLK
CLK
nCLK
CLK
nCLK
3.3V
3.3V
Differential
Input
3.3V
Differential
Input
Receiver