ICS307M-02ILFT IDT, Integrated Device Technology Inc, ICS307M-02ILFT Datasheet - Page 4
![IC CLOCK SOURCE PROGR 16-SOIC](/photos/6/53/65328/ics307m-02ilft_sml.jpg)
ICS307M-02ILFT
Manufacturer Part Number
ICS307M-02ILFT
Description
IC CLOCK SOURCE PROGR 16-SOIC
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Generatorr
Datasheet
1.ICS307M-02LFT.pdf
(10 pages)
Specifications of ICS307M-02ILFT
Pll
Yes with Bypass
Input
Clock, Crystal
Output
LVCMOS
Number Of Circuits
1
Ratio - Input:output
2:2
Differential - Input:output
No/No
Frequency - Max
180MHz
Divider/multiplier
Yes/No
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SOIC
Frequency-max
180MHz
Number Of Elements
1
Pll Input Freq (min)
2MHz
Pll Input Freq (max)
50MHz
Operating Supply Voltage (typ)
3.3/5V
Operating Temp Range
-40C to 85C
Package Type
SOIC N
Output Frequency Range
6 to 180MHz
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Pin Count
16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
307M-02ILFT
800-1797-2
800-1797-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS307M-02ILFT
Manufacturer:
ADI
Quantity:
211
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
ICS307-01/-02
SERIALLY PROGRAMMABLE CLOCK SOURCE
Setting the Device Characteristics
The tables below show the settings which can be configured, as well as the VCO and Reference dividers.
Table 1. Output Divide and Maximum Output Frequency
Table 2. CLK2 Output
Table 3. Output Duty Cycle Configuration
Table 4. Crystal Load Capacitance
Note: The TTL bit optimizes the duty cycle at different VDD. When VDD is 5 V, set to 0 for a near-50% duty
cycle with TTL levels. When VDD is 3.3 V, set this bit to 1 so the 50% duty cycle is achieved at VDD/2.
Note: f is the crystal frequency in MHz between 10 and 27 MHz. Effective load capacitance will be higher
for crystal frequencies lower than 10 MHz. If a clock input is used, set C1 = 0 and C0 = 0.
S2
F1
0
0
0
0
1
1
1
1
0
0
1
1
TTL
C1
0
1
0
0
1
1
S1
F0
0
0
1
1
0
0
1
1
0
1
0
1
C0
0
1
0
1
S0
0
1
0
1
0
1
0
1
Duty Cycle Measured At
OFF (Low)
F
F
CLK2
CLK1
REF
REF
CLK1 Output
/2
/2
Divide
VDD/2
1.4 V
10
2
8
4
5
7
3
6
22.3 - 0.083 f
23.1 - 0.093 f
23.7 - 0.106 f
24.4 - 0.120 f
VDD = 5V
5 V or 3.3 V (MHz)
Max. Frequency
200
100
135
40
50
80
55
67
Recommended VDD
4
22.1 - 0.094 f
22.9 - 0.108 f
23.5 - 0.120 f
24.2 - 0.135 f
VDD = 3.3V
3.3 V
5 V
Industrial Temp. Version
Max. Frequency
180
120
36
45
90
72
50
60
SER PROG CLOCK SYNTHESIZER
ICS307-01/-02 REV J 051310