ICS307-02 ICST [Integrated Circuit Systems], ICS307-02 Datasheet

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ICS307-02

Manufacturer Part Number
ICS307-02
Description
SERIALLY PROGRAMMABLE CLOCK SOURCE
Manufacturer
ICST [Integrated Circuit Systems]
Datasheet
MDS 307-01/02 F
I n t e gra te d C i r c u i t S y s t e m s
Description
The ICS307-01 and ICS307-02 are versatile serially
programmable clock sources which take up very little
board space. They can generate any frequency from 6
to 200 MHz and have a second configurable output.
The outputs can be reprogrammed on the fly and will
lock to a new frequency in 10 ms or less. Smooth
transitions (in which the clock duty cycle remains near
50%) are guaranteed if the output divider is not
changed.
The devices includes a PDTS pin which tri-states the
output clocks and powers down the entire chip.
The ICS307-02 features a default clock output at
start-up and is recommended for all new designs.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
For applications which require defined input to output
skew, use the ICS527-01.
Block Diagram
clock input
Crystal or
Optional crystal capacitors
X1/ICLK
X2
STROBE
DATA
SCLK
Oscillator
Crystal
Register
Shift
5 25 Race Stre et, San Jo se, CA 9 5126
R6:R7
9
2
3
2
7
Reference
Divider
S2:S0
TTL
V8:V0
C1:C0
F1:F0
S
ERIALLY
Phase Comparator,
Charge Pump, and
1
Loop Filter
Divider
VCO
P
Features
ROGRAMMABLE
Packaged in 16-pin (150 mil wide) SOIC
ICS307M-02 and -02I available in Pb (lead) free
package
Highly accurate frequency generation
Serially programmable: user determines the output
frequency via a 3 wire interface
Eliminates need for custom quartz
Input crystal frequency of 5 - 27 MHz
Output clock frequencies up to 200 MHz
Power down tri-state mode
Very low jitter
Operating voltage of 3.3 V or 5 V
25 mA drive capability at TTL levels
Industrial temperature version available
GND
VDD
VCO
te l (40 8) 2 97-12 01
Output
Divider
S2:S0
3
ICS307-01/02
C
LOCK
Function
F1:F0
Select
3
w w w. i c st . c o m
Revision 121304
S
OURCE
PDTS
CLK1
CLK2

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ICS307-02 Summary of contents

Page 1

... The devices includes a PDTS pin which tri-states the output clocks and powers down the entire chip. The ICS307-02 features a default clock output at start-up and is recommended for all new designs. This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed ...

Page 2

... No connect. Do not connect anything to this pin connect. Do not connect anything to this pin. Input crystal connection. Connect to a crystal or leave unconnected for clock XO input. 2 ICS307-01/ ROGRAMMABLE LOCK Pin Description Revision 121304 tel (4 08) 297 -1 201 ● ...

Page 3

... CLK1 will always have some clock signal present, but CLK2 could possibly be OFF (low). The ICS307-02 on-chip registers are initially configured to provide a x1 output clock on both the CLK1 and CLK2 outputs. The output frequency will be the same as the input clock or crystal ...

Page 4

... V or 3.3 V (MHz) Industrial Temp. Version 40 200 50 100 80 55 135 67 Recommended VDD 5 V 3.3 V VDD = 5V VDD = 3.3V 22.1 - 0.094 f 22.9 - 0.108 f 23.5 - 0.120 f 24.2 - 0.135 f 4 ICS307-01/ ROGRAMMABLE LOCK Max. Frequency 36 180 120 60 Revision 121304 tel (4 08) 297 -1 201 ● ● S ...

Page 5

... The ICS307 can be reprogrammed at any time during operation. If R6:0, V8:0, TTL, or C1:0 are changed, the frequency will transition smoothly to the new value over about 1 ms, without glitches or short cycles. If S2:0 is changed possible to generate glitches on CLK1 and also on CLK2 for F1 Changing F1:0 will generate glitches on CLK2. Power up default values for ICS307- ...

Page 6

... The ICS307 requires a 0.01µF decoupling capacitor to be connected between VDD and GND. It must be connected close to the ICS307 to minimize lead inductance. A 33Ω terminating resistor can be used in series with CLK1 and CLK2 outputs. A parallel resonant, fundamental mode crystal with a load (correlation) capacitance of C should be used, where C is the value calculated from Table 4 ...

Page 7

... Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS307-01/02. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied ...

Page 8

... STROBE goes high until CLK out t Deviation from mean ja Symbol Conditions θ Still air JA θ 1 m/s air flow JA θ 3 m/s air flow JA θ ICS307-01/ ROGRAMMABLE LOCK OURCE Min. Typ. Max. Units ±70 4 270 Min. Typ. Max. Units 5 27 ...

Page 9

... ICS307M-02 ICS307M-02T ICS307M-02 ICS307M-02LF ICS307M-02LF ICS307M-02LFT ICS307M-02LF ICS307M-02I ICS307M-02I ICS307M-02IT ICS307M-02I ICS307M-02ILF ICS307M02ILF ICS307M-02ILFT ICS307M02ILF While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use ...

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