FPD85310VJD National Semiconductor, FPD85310VJD Datasheet - Page 25

• Manufacturer Part Number: FPD85310VJD
• Description: IC CTRLR PANEL TIMING 100-TQFP
• Manufacturer: National Semiconductor
• Type: Panel Timing Controllerr

Specifications of FPD85310VJD

• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Frequency-max: -
• Output: -
• Input: -
• Other names: *FPD85310VJD

APPENDIX A: GPO Programming Examples
GPO Programming Example #1:
Generate a control signal which transitions high at the end of
each line, has a pulsewidth of 3 µs, and remains low during
the vertical blanking period. This control is used for the latch
pulse to the column drivers.
Vertical control is active beginning at line 1 and remains ac-
tive for 768 lines.
GPO Vertical Start Register = 1
GPO Vertical Duration Register = 768d (300h)
Positive pulse goes high each line at output clock 512 corre-
sponding to when the last two pixels are output on OR, OG,
OB, ER, EG, EB. Pulse remains high for 98 output clocks (98
x 30.8 ns/clock = 3.02 µs). (Dual Bus output clock =
32.5 MHz for 65 MHz XGA video, 1024 pixels/line, 768 dis-
played lines/frame).
Note: 6 counts are added to the output start # because the GPO pixel count
GPO Horizontal Start Register = 518d (206h)
GPO Horizontal Duration Register = 98d (62h)
The control pulses are positive (bit [0] = 0) and the toggle cir-
cuitry is disabled (bit1 [1] = 0).
GPO Control Register = 0
begins 6 clocks prior to the output data.
25
Horizontal time (clocks/line) = 1300 dot clocks
Vertical period (lines/frame) = 850 lines
(Continued)
DS101086-23
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