FPD85310VJD National Semiconductor, FPD85310VJD Datasheet
FPD85310VJD
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FPD85310VJD Summary of contents
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... The system can access the EEPROM to read the display identification data or pro- gram initialization values used by the FPD85310. System Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS101086 September 1999 Features n FPD-Link System Interface utilizes Low Voltage Differential Signaling (LVDS) ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT Storage Temperature Range (T ) STG Lead Temperature ( (Soldering 10 sec.) DC Electrical Characteristics Symbol Parameter V Minimum High Level ...
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Device Specifications = 0˚C to 70˚ Note 3: Measurements DIFF Note 4: RCCS measured between earliest and latest LVDS edges ± Note 5: * RxIN3 pair (RxIN_3 ) is option for 24-bit color ...
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Device Specifications T A Internal Pixel Count final value = pixels per line/2 Maximum Internal Pixel Count = 1024 (32.5 MHz clocks) Internal Pixel Count is used to generate the horizontal_component for GPO generation See Figure 9 ** Without Blanking ...
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Device Specifications = 0˚C to 70˚ lines per frame count, LCmax = 2048 lines Internal Line Count is used to generate the vertical component for GPO generation See Figure 9 FIGURE 8. Internal Line Count ...
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Device Specifications T A Vertical Backporch = 35 Lines/Frame = 825 Pixels/Line = 1200 Horizontal Backporch = 100 Displayed pixels/line = 1024 (Valid data during ENAB High time) Displayed lines/frames = 768 Frequency = 65 MHz (or less) Block Diagram ...
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Functional Description FPD-LINK RECEIVER The LVDS based FPD-Link Receiver receives inputs video data and control timing. Four LVDS channels plus clock pro- vide 24-bit color. Three LVDS channels can be used for 18-bit color. The video data is regenerated to ...
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Functional Description face or custom gate interfaces can be implemented with the nine GPOs. Note that GPO [8] must be used for output blanking control. Five registers provide the timing definition for each GPO. The Horizontal Start register defines the ...
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Functional Description (Continued) INPUT FORMAT FIXED VERTICAL, FIXED HORIZONTAL determined by the INPUT CONTROL REGISTER bits [1:0] FIXED VERTICAL, FIXED HORIZONTAL (FIX VERTICAL = 1, FIX HORIZONTAL = 1) FIXED VERTICAL, ENAB HORIZONTAL (FIXED VERTICAL = 1, FIXED HORIZONTAL = ...
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Functional Description PROGRAMMABLE REGISTERS At power-up, data is read from an external EEPROM. If any- thing other than 00H is read back on the first EEPROM ac- cess (indicating EEPROM not present), the internal default TABLE 2. FPD85310 Programmable Register ...
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Functional Description (Continued) TABLE 2. FPD85310 Programmable Register Definition (Continued) Control EEPROM The control registers provide mode setting information to the input and output interfaces. Registers Address Output DB [0] OCLK Enable (1-On, 0-TRI-STATE) Enable/Polarity [1] OCLK Polarity (1-Per Datasheet, ...
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Functional Description (Continued) TABLE 2. FPD85310 Programmable Register Definition (Continued) Control EEPROM The control registers provide mode setting information to the input and output interfaces. Registers Address [3] [4] [6:5] [7] Vertical DA HSYNCS from VSYNC falling ...
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Functional Description (Continued) TABLE 2. FPD85310 Programmable Register Definition (Continued) Control EEPROM The control registers provide mode setting information to the input and output interfaces. Registers Address Control Register [0]. Output polarity - defines active high or active low output ...
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Functional Description (Continued) TABLE 3. EEPROM Memory Map (Continued) Address 94,93 gpo [6]_pstart_reg (10) 96,95 gpo [6]_pcount_reg (11) 98,97 gpo [6]_lstart_reg (11) 9A,99 gpo [6]_lcount_reg (11) 9B gpo [6]_cont_reg (5) 9D,9C gpo [5]_pstart_reg (10) 9F,9E gpo [5]_pcount_reg (11) A1,A0 gpo ...
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Functional Description (Continued) TABLE 3. EEPROM Memory Map (Continued) Address D8,D7 hbp_reg (11) DA,D9 vbp_reg (11) DB output_enable/polarity_control (8) FF–DC not used/not loaded Note 7: Programmable CD Size “n” (up to 128) Note 8: One or both clocks can be ...
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Functional Description Note 11: Programmable CD Size “n” (up to 128) Note 12: Data skewed to reduce simultaneous switching FIGURE 11. Dual Bus Single Port Column Driver Interface www.national.com (Continued) (Skewed outputs) 16 DS101086-5 ...
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Functional Description (Continued) Note 13: One or both clocks can be used Note 14: Unused clock can be turned off FIGURE 12. Dual Bus Dual Port Column Driver Interface (Non-skewed outputs) 17 DS101086-6 www.national.com ...
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Functional Description Note 15: Data skewed to reduce simultaneous switching FIGURE 13. Dual Bus Dual Port Column Driver Interface www.national.com (Continued) (Skewed outputs) 18 DS101086-7 ...
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Functional Description (Continued) Note 16: ECLK/ERGB not used — These outputs can be disabled by setting bits 2 and 5 to “0” in the Output Enable/Polarity Control register. Note 17: Start pulse offset * (D3 [1:0]) is defined as below ...
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Functional Description Note 21: RSTZ transition Low-to-High occurs at the completion of the RPLLS delay or later as shown above. Note 22: All outputs* forced low in default timing of FPD85310 during power-up delay time. Note 23: All outputs ** ...
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Functional Description (Continued) FIGURE 17. Delay Circuit for Stable RSTZ FAILURE DETECTION Mode Fix Vertical/Horizontal Fix Vertical/ENAB Horizontal ENAB Only Mode (1) Wait ( 2) ms then output 2048 pixels/line and 2047 lines/frame. No esp/osp. No eclk/oclk. (2) Wait ( ...
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... RXIN_1 ± 2 RXIN_2 ± 2 RXIN_3 ± 2 RXCLK 1 RSTZ 1 SPDZ www.national.com Order Number FPD85310VJD See NS Package Number VJD100A I/O LVDI FPD-Link data pair 0 LVDI FPD-Link data pair 1 LVDI FPD-Link data pair 2 LVDI FPD-Link data pair 3 (used in 8-bit video applications) LVDI FPD-Link Clock I ...
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Pin Description (Continued) Pin No: Pin Name Pin Count COLUMN DRIVER INTERFACE 1 ECLK 1 ESP 6 ER0..ER5 6 EG0..EG5 6 EB0..EB5 1 EPOL 1 OCLK 1 OSP 6 OR0..OR5 6 OG0..OG5 6 OB0..OB5 1 OPOL GENERAL PURPOSE OUTPUTS 9 ...
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APPENDIX A: GPO Programming Examples The GPO control generation is based on the internal line count and pixel count shown in Figure 7 and Figure 8 . Two programmable registers (Vertical Start and Vertical Duration) control the vertical component of ...
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APPENDIX A: GPO Programming Examples GPO Programming Example #1: Generate a control signal which transitions high at the end of each line, has a pulsewidth of 3 µs, and remains low during the vertical blanking period. This control is used ...
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APPENDIX A: GPO Programming Examples (Continued) GPO Programming Example #2: Generate a control signal which transitions low 20 output clocks after the beginning of each output line, has a pulse- width (low µs, and goes high during horizontal ...
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APPENDIX A: GPO Programming Examples (Continued) GPO Programming Example #3: Generate a control signal which toggles during horizontal blanking and alternates polarity each frame. This control sig- nal is used as the reversal signal. Control is active beginning at line ...
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... APPENDIX B: National Semiconductor FPD85310 REQUEST FORM OF MASK VERSION Company Name:_________________________________Dept:______________________ Tel: _____________________ Model Name (Application): ______________________________________________ Register Values: TABLE 6. Register Values for GPO[0:8]’s Programming Pin Name Address 81 82 GPO8 Value Address 8A 8B GPO7 Value Address 93 94 GPO6 Value Address 9C 9D ...
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... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...