ICS9DB803DFLF IDT, Integrated Device Technology Inc, ICS9DB803DFLF Datasheet - Page 4

• Manufacturer Part Number: ICS9DB803DFLF
• Description: IC BUFFER 8OUTPUT DIFF 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Bufferr
• Series: -r

Specifications of ICS9DB803DFLF

• Input: HCSL
• Output: HCSL, LVDS
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Frequency-max: 400MHz
• Number Of Elements: 1
• Supply Current: 200mA
• Pll Input Freq (min): 50MHz
• Pll Input Freq (max): 110MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: SSOP
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 9DB803DFLF

Pin Description for OE_INV = 0
IDT
PIN #
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
ICS9DB803D
Eight Output Differential Buffer for PCIe for Gen 2
TM
/ICS
GND
PD#
DIF_STOP#
HIGH_BW#
DIF_4#
DIF_4
VDD
GND
DIF_5#
DIF_5
OE_5
OE_6
DIF_6#
DIF_6
VDD
OE_INV
DIF_7#
DIF_7
OE_4
OE_7
LOCK
IREF
GNDA
VDDA
TM
PIN NAME
Eight Output Differential Buffer for PCIe Gen 2
PIN TYPE
PWR
PWR
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
Ground pin.
Asynchronous active low input pin used to power down the device.
The internal clocks are disabled and the VCO and the crystal are
stopped.
Active low input to stop differential output clocks.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
0.7V differential complement clock output
0.7V differential true clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential complement clock output
0.7V differential true clock output
Active high input for enabling output 5.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling output 6.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
0.7V differential complement clock output
0.7V differential true clock output
Active high input for enabling output 4.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling output 7.
0 = tri-state outputs, 1= enable outputs
3.3V output indicating PLL Lock Status. This pin goes high when
lock is achieved.
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
4
DESCRIPTION
ICS9DB803D
REV J 01/27/11