ICS9DB803DFLF IDT, Integrated Device Technology Inc, ICS9DB803DFLF Datasheet - Page 17

• Manufacturer Part Number: ICS9DB803DFLF
• Description: IC BUFFER 8OUTPUT DIFF 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Bufferr
• Series: -r

Specifications of ICS9DB803DFLF

• Input: HCSL
• Output: HCSL, LVDS
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Frequency-max: 400MHz
• Number Of Elements: 1
• Supply Current: 200mA
• Pll Input Freq (min): 50MHz
• Pll Input Freq (max): 110MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: SSOP
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 9DB803DFLF

SRC_STOP#
The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must
be present on SRC_IN for this input to work properly. The SRC_STOP# signal is de-bounced and must remain stable for two
consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion.
SRC_STOP# - Assertion
Asserting SRC_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output
to stop). When the SRC_STOP# drive bit is ‘0’, the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There
is no change in output drive current. DIF is driven with 6xI
SRC_STOP# drive bit is ‘1’, the final state of all DIF output pins is Low. Both DIF and DIF# are not driven.
SRC_STOP# - De-assertion (transition from '0' to '1')
All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs is
2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the SRC_STOP# drive control bit is ‘1’ (tri-state), all
stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion.
SRC_STOP_1 (SRC_Stop = Driven, PD = Driven)
SRC_STOP_2 (SRC_Stop =Tristate, PD = Driven)
IDT
ICS9DB803D
Eight Output Differential Buffer for PCIe for Gen 2
TM
/ICS
TM
Eight Output Differential Buffer for PCIe Gen 2
DIF# (Free Running)
DIF (Free Running)
DIF# (Free Running)
DIF (Free Running)
DIF# (Stoppable)
DIF (Stoppable)
DIF# (Stoppable)
DIF (Stoppable)
SRC_Stop#
PWRDWN#
SRC_Stop#
PWRDWN#
REF.
DIF# is not driven, but pulled low by the termination. When the
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1mS
1mS
ICS9DB803D
REV J 01/27/11