ICS93722CFLF IDT, Integrated Device Technology Inc, ICS93722CFLF Datasheet - Page 5

• Manufacturer Part Number: ICS93722CFLF
• Description: IC DDR PLL ZD BUFFER 28-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Zero Delay Bufferr

Specifications of ICS93722CFLF

• Input: Clock
• Output: Clock
• Frequency - Max: 200MHz
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 93722CFLF

IDT
93722
Low Cost DDR Phase Lock Loop Zero Delay Buffer
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D4
• IDT clock will acknowledge
• Controller (host) sends a dummy command code
• IDT clock will acknowledge
• Controller (host) sends a dummy byte count
• IDT clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
• IDT clock will acknowledge each byte one at a
time .
• Controller (host) sends a Stop bit
Notes:
1.
2.
3.
4.
5.
6.
®
Low Cost DDR Phase Lock Loop Zero Delay Buffer
through byte 6
The IDT clock generator is a slave/receiver, I
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes.
The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
Dummy Command Code
Dummy Byte Count
Controller (Host)
Address
Start Bit
Stop Bit
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
D4
(H)
How to Write:
For more information, contact IDT for an I
The information in this section assumes familiarity with I
General I
IDT (Slave/Receiver)
2
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes
2
C serial interface information
(H)
2
C component. It can read back the data stored in the latches for
2
C programming application note.
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D5
• IDT clock will acknowledge
• IDT clock will send the byte count
• Controller (host) acknowledges
• IDT clock sends first byte (Byte 0) through byte 7
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
Controller (Host)
2
Address
C programming.
Start Bit
Stop Bit
D5
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
(H)
How to Read:
IDT (Slave/Receiver)
Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
ACK
93722
REV G 10/05/10
(H)