ICS93722CFLF IDT, Integrated Device Technology Inc, ICS93722CFLF Datasheet - Page 4

• Manufacturer Part Number: ICS93722CFLF
• Description: IC DDR PLL ZD BUFFER 28-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Zero Delay Bufferr

Specifications of ICS93722CFLF

• Input: Clock
• Output: Clock
• Frequency - Max: 200MHz
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 93722CFLF

Recommended Operating Condition (see note 1)
Timing Requirements
Switching Characteristics
IDT
Analog / Core Supply Voltage
T
T
1. Guaranteed by design, not 100% tested in production.
T
1. Guaranteed by design, not 100% tested in production.
2. Refers to transistion on non-inverting output.
3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies.
Operating Clock Frequency
A
A
A
93722
Low Cost DDR Phase Lock Loop Zero Delay Buffer
Duty Cycle (differential)
®
= 0 - 70°C; Supply Voltage AV
= 0 - 70°C; Supply Voltage AV
= 0 - 70°C; Supply Voltage V
Output to output Skew
This is due to the formula: duty cycle = t
Input Clock Duty Cycle
Cycle to cycle Jitter
Rise Time, Fall Time
Low Cost DDR Phase Lock Loop Zero Delay Buffer
Input Voltage Level
Clock Stabilization
Inpu Duty Cycle
Absolute Jitter
Input max jitter
PARAMETER
PARAMETER
PARAMETER
Phase Error
Pulse Skew
1
1
1
1,2
1
1
1
1,3
1
1
DD
V
SYMBOL
SYMBOL
t
(phase error)
DD
DD
DD
SYMBOL
T
T
= 2.5 V +/-0.2V (unless otherwise stated)
I
T
t
T
, V
TCYC
, V
cyc-cyc
V
freq
R
, AV
V
I
skewp
D
t
skew
DC
jabs
, t
STAB
d
IH
IL
C
DD
DD
tin
F
op
DD
= 2.5 V +/-0.2V (unless otherwise stated)
= 2.5 V +/-0.2V (unless otherwise stated)
wH
/ t
C
from V
, where the cycle time (t
CONDITIONS
V
V
T
T
= 50%, 101 MHz to 167 MHz
= 50%, 66 MHz to 100 MHz
DD
Single-ended 20 - 80 %
CONDITIONS
Load = 120
CLK_INT to FB_INT
= 2.5V to 1% target
frequency
100 - 200 MHz
100 - 200 MHz
CONDITIONS
V
66 MHz
66 MHz
T
= 50%
/ 12 pF
C
V
) decreases as the frequency increases.
DD
/2 + 0.5V
MIN
2.3
40
MIN
66
40
TYP
2.5
TYP
-150
49.5
MIN
450
49
V
DD
MAX
93722
200
100
60
MAX
/2 - 0.5V
TYP
550
500
2.7
50
25
50
70
50
50
60
REV G 10/05/10
UNITS
MAX
MHz
50.5
120
110
150
100
100
950
75
65
51
%
s
UNITS
ps
V
V
V
UNITS
ps
ps
ps
ps
ps
ps
%