ICS93722CFLF IDT, Integrated Device Technology Inc, ICS93722CFLF Datasheet - Page 2

• Manufacturer Part Number: ICS93722CFLF
• Description: IC DDR PLL ZD BUFFER 28-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Zero Delay Bufferr

Specifications of ICS93722CFLF

• Input: Clock
• Output: Clock
• Frequency - Max: 200MHz
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 93722CFLF

Pin Description
Bytes 0 to 4 are reserved power up default = 1.
Byte 5: Output Control
(1= enable, 0 = disable)
Note: PWD = Power Up Default
Byte 6: Output Control
(1= enable, 0 = disable)
IDT
26, 24, 17, 13, 4, 2 CLKT(5:0)
27, 25, 16, 14, 5, 1 CLKC(5:0)
93722
Low Cost DDR Phase Lock Loop Zero Delay Buffer
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
®
PIN NUMBER
Bit
6, 11, 15, 28
Low Cost DDR Phase Lock Loop Zero Delay Buffer
3, 12, 23
9, 18, 21
20
22
10
19
7
8
24, 25
26, 27
PIN#
GND
SCLK
CLK_INT
N/C
FB_OUTT
FB_INT
SDATA
VDD
VDDA
PWD
PIN NAME
1
1
1
1
1
1
1
1
DESCRIPTION
CLK4 (T&C)
CLK5 (T&C)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TYPE
PWR
PWR
PWR
OUT
OUT
OUT
IN
IN
IN
IN
-
"Complementary" clocks of differential pair outputs.
"True" Clock of differential pair outputs.
Power supply 2.5V
"True" reference clock input
Not connected
"True" Feedback output, dedicated for external feedback. It switches at
"True" Feedback input, provides feedback signal to the internal PLL for
Data input for I
Ground
Clock input of I
Analog power supply, 2.5V
the same frequency as the CLK. This output must be wired to FB_INT.
synchronization with CLK_INT to eliminate phase error.
2
2
C serial input, 5V tolerant input
C input, 5V tolerant input
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit
13, 14
17, 16
DESCRIPTION
PIN#
2, 1
4, 5
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
CLK0 (T&C)
CLK1 (T&C)
CLK2 (T&C)
CLK3 (T&C)
Reserved
Reserved
Reserved
Reserved
93722
REV G 10/05/10