ICS93722CFLF IDT, Integrated Device Technology Inc, ICS93722CFLF Datasheet

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ICS93722CFLF

Manufacturer Part Number
ICS93722CFLF
Description
IC DDR PLL ZD BUFFER 28-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Zero Delay Bufferr
Datasheet

Specifications of ICS93722CFLF

Input
Clock
Output
Clock
Frequency - Max
200MHz
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
28-SSOP
Frequency-max
200MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
93722CFLF
Low Cost DDR Phase Lock Loop Zero Delay Buffer
Description
DDR Zero Delay Clock Buffer
Output Features
Key Specifications
Functional Block Diagram
CLK_INT
CLK_INT
IDT
FB_INT
FB_INT
SD
SDA A T T A A
SCLK
SCLK
®
PEAK - PEAK jitter (66MHz): <120ps
PEAK - PEAK jitter (>100MHz): <75ps
CYCLE - CYCLE jitter (66MHz):<110ps
CYCLE - CYCLE jitter (>100MHz):<65ps
OUTPUT - OUTPUT skew: <100ps
Output Rise and Fall Time: 650ps - 950ps
DUTY CYCLE: 49.5% - 50.5%
Low Cost DDR Phase Lock Loop Zero Delay Buffer
Low skew, low jitter PLL clock driver
I
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
3.3V tolerant CLK_INT input
2
C for functional and output control
Control
Control
Logic
Logic
PLL
PLL
FB_OUTT
FB_OUTT
CLKT0
CLKT0
CLKC0
CLKC0
CLKT1
CLKT1
CLKC1
CLKC1
CLKT2
CLKT2
CLKC2
CLKC2
CLKT3
CLKT3
CLKC3
CLKC3
CLKT4
CLKT4
CLKC4
CLKC4
CLKT5
CLKT5
CLKC5
CLKC5
Pin Configuration
Functionality Table
AVDD
(nom)
(nom)
(nom)
GND
GND
2.5V
2.5V
2.5V
INPUTS
CLK_INT
CLK_INT
<20MHz
CLKC0
CLKC1
CLKC2
CLKT0
CLKT1
CLKT2
VDDA
SCLK
L
H
L
H
GND
GND
VDD
VDD
N/C
CLKT
H
Z
H
L
L
10
11
12
13
14
OUTPUTS
1
2
3
4
5
6
7
8
9
CLKC FB_OUT
28-Pin SSOP
H
Z
H
L
L
H
Z
H
L
L
Bypassed/off
Bypassed/off
PLL State
28
27
26
25
24
23
22
21
20
19
18
17
16
15
93722
on
on
off
DATASHEET
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
N/C
FB_INT
FB_OUTT
N/C
CLKT3
CLKC3
GND
REV G 10/05/10
93722

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ICS93722CFLF Summary of contents

Page 1

Low Cost DDR Phase Lock Loop Zero Delay Buffer Description DDR Zero Delay Clock Buffer Output Features • Low skew, low jitter PLL clock driver 2 • for functional and output control • Feedback pins for input to ...

Page 2

Low Cost DDR Phase Lock Loop Zero Delay Buffer Pin Description PIN NUMBER PIN NAME 6, 11, 15, 28 GND 27, 25, 16, 14 CLKC(5:0) 26, 24, 17, 13 CLKT(5:0) 3, 12, 23 VDD SCLK ...

Page 3

Low Cost DDR Phase Lock Loop Zero Delay Buffer Absolute Max Supply Voltage (VDD & AVDD) Logic Inputs Ambient Operating Temperature Case Temperature Storage Temperature Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the ...

Page 4

Low Cost DDR Phase Lock Loop Zero Delay Buffer Recommended Operating Condition (see note 70°C; Supply Voltage PARAMETER SYMBOL V Analog / Core Supply Voltage DD Input Voltage Level Inpu Duty ...

Page 5

Low Cost DDR Phase Lock Loop Zero Delay Buffer General I The information in this section assumes familiarity with I For more information, contact IDT for an I How to Write: • Controller (host) sends a start bit. • ...

Page 6

Low Cost DDR Phase Lock Loop Zero Delay Buffer N E1 INDEX INDEX AREA AREA 209 mil SSOP Ordering Information 93722yFLFT Example: XXXX ® IDT ...

Page 7

Dual Channel DDR II Zero Delay Buffer Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United ...

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