IDTCV133PAG IDT, Integrated Device Technology Inc, IDTCV133PAG Datasheet - Page 17

• Manufacturer Part Number: IDTCV133PAG
• Description: IC FLEXPC CLK PROGR P4 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: FlexPC™r
• Type: PC Clockr

Specifications of IDTCV133PAG

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: CV133PAG

CPU STOP FUNCTIONALITY
CPU_STOP# ASSERTION (TRANSITION FROM ‘1’ TO ‘0’)
to the CPU output of interest is programmed to a ‘0’, CPU output will stop CPU_True = High and CPU_Complement = Low. When the SMBus CPU_STOP#
tri-state bit corresponding to the CPU output of interest is programmed to a ‘1’, CPU outputs will be tri-stated.
CPU_STOP# - DE-ASSERTION (TRANSITION FROM ‘0’ TO ‘1’)
is two to six CPU clock periods. If the control register tristate bit corresponding to the output of interest is programmed to ‘1’, then the stopped CPU outputs will
be driven High within 10nS of CPU_STOP# de-assertion to a voltage greater than 200mV.
IDTCV133
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
CPU_STOP#
The CPU_STOP# signal is an active low input controlling the CPU outputs. This signal can be asserted asynchronously.
Asserting CPU_STOP# pin stops all CPU outputs that are set to be stoppable after their next transition. When the SMBus CPU_STOP tri-state bit corresponding
With the de-assertion of CPU_STOP# all stopped CPU outputs will resume without a glitch. The maximum latency from the de-assertion to active outputs
1
0
I
REF
Normal
* 6 or float
CPU
Normal
CPU#
Low
CPU_STOP#
CPU_STOP#
CPU Internal
CPU#
CPU
CPU#
CPU
Normal
Normal
SRC
Normal
Normal
10nS > 200mV
t
SRC#
DRIVE
_CPU_Stop
17
PCIF/PCI
33MHz
33MHz
48MHz
48MHz
USB
COMMERCIAL TEMPERATURE RANGE
DOT96
Normal
Normal
DOT96#
Normal
Normal
14.318MHz
14.318MHz
REF