ML610Q422-NNNTBZ03A7 Rohm Semiconductor, ML610Q422-NNNTBZ03A7 Datasheet - Page 358

• Manufacturer Part Number: ML610Q422-NNNTBZ03A7
• Description: MCU 8BIT 32K FLASH 22CH 120-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q422-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.3.3
When the programmable display allocation function is used (DASN bit of DSPMOD1 register is “1”), display registers
(DSPR00 to 71) segment mapping can be set in bit units according to the contents of display allocation registers A and B
(DSmCnA, DSmCnB: m = 0 to 49, n = 0 to 7).
Table 26-7 shows the frame frequencies and the duty conditions that allow the use of the programmable allocation function.
Note:
- When the duty is other than those indicated in Table 26-6, the programmable allocation function can not be used
regardless of the content of the DASN bit of DSPMOD1. The programmable display allocation function is available only
when 1/1~1/8 duty is selected (when using eight COMs or less for display), it does not work when 1/9~1/16 duty is
selected (when using nine COMs or more for display).
- Select type 3 for the display register segment map (Set DADM1 bit of DSPMOD1 register to “1”) when using the
programmable allocation function.
Figure 26-8 shows the configuration when using the programmable display allocation function.
0F5F1H
0F5F0H
0F402H
0F401H
0F400H
Display allocation register A
Data bus
Figure 26-8 Configuration When Using the Programmable Display Allocation Function
Segment Mapping When the Programmable Display Allocation Function is Used
Table 26-6 Conditions That Allow the Use of Programmable Allocation Function
DS49C7A
DS48C7A
DS2C0A
DS1C0A
DS0C0A
8
Specifies the
addresses of a
display register
Frame frequency
Approx. 102 Hz
Approx. 64 Hz
Approx. 73 Hz
Approx. 85 Hz
Mapping specification of SEG63-COM7
Mapping specification of SEG62-COM7
Mapping specification of SEG2-COM0
Mapping specification of SEG1-COM0
Mapping specification of SEG0-COM0
Display register
DSPR71
DSPR00
|
Duty that allows the use of duty
26 – 27
8
Display allocation register B
1/1 to 1/8 Duty
1/1 to 1/8 Duty
1/1 to 1/7 Duty
1/1 to 1/6 Duty
DS49C7B
DS48C7B
DS2C0B
DS1C0B
DS0C0B
Selector
3
ML610Q421/ML610Q422 User’s Manual
Specifies a bit of
a display register
0F7FFH
0F7FEH
0F602H
0F601H
0F600H
1
Chapter 26 LCD Drivers
Segment
drivers
SEG49
SEG48
SEG2
SEG1
SEG0