ML610Q422-NNNTBZ03A7 Rohm Semiconductor, ML610Q422-NNNTBZ03A7 Datasheet - Page 121

• Manufacturer Part Number: ML610Q422-NNNTBZ03A7
• Description: MCU 8BIT 32K FLASH 22CH 120-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q422-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ML610Q421/ML610Q422 User’s Manual
Chapter 8 Capture
8.3
Description of Operation
The capture circuit starts the capture operation by setting the ECAP0 or ECAP1 bit of the capture control register
(CAPCON).
When the input trigger from the P00 or P01 pin selected by the external interrupt control register 0 or 1 (EXICON0 or
EXICON1) is generated and the P00 or P01 interrupt request flag (QP00 or QP01) is set to “1”, the T4KHZ to T32HZ
signals of the low-speed time base counter (LTBC) are captured in the capture register 0 or 1 (CAPR0 or CAPR1) on the
next low-speed clock (LSCLK) falling edge and the at the same time, the capture flag (CAPF0 or CAPF1) of the capture
status register (CAPSTAT) is set to “1”.
When the capture flag (CAPF0, CAPF1) is “1”, the following capture operation stops.
After reading the value captured in the capture register 0 or 1 (CAPR0, CAPR1), perform write operation (write data is
meaningless) for the capture register 0 or 1 (CAPR0, CAPR1), clear the capture flag (CAPF0, CAPF1) to “0”, and wait
for the next P00 or P01 interrupt.
Figure 8-2 shows the timing of the capture operation.
System clock
SYSCLK
LSCLK
(32.768 kHz)
LT BC
N
N+1
(T4KHZ to T32HZ)
P00 and P01 pins
QP00, QP01
Interrupt request flag
CAPR0, CAPR1
XX
N+1
N+1
CAPF0, CAPF1
Write CAPR0, 1
Figure 8-2 Timing Diagram of Capture Operation
Note:
When CPU is operating at the high speed (HSCLK), check that the capture flag (CAPF0, CAPF1) is set to "1" after the
P00 or P01 interrupt request is generated and then read capture data register 0 or 1 (CAPR0, CAPR1).
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