ML610Q422-NNNTBZ03A7 Rohm Semiconductor, ML610Q422-NNNTBZ03A7 Datasheet
ML610Q422-NNNTBZ03A7
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ML610Q422-NNNTBZ03A7 Summary of contents
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... ML610Q421/ML610Q422 User’s Manual FEUL610Q421-04 Issue Date: Dec 3, 2010 ...
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NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application ...
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... Description on the integrated development environment uEASE User’s Manual Description on the on-chip debug tool uEASE. uEASE connection Manual for ML610Q421/ML610Q422 Description about the connection between uEASE and FWuEASE Flash Writer Host Program User’s Manual Description on the Flash Writer host program. ...
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Classification Notation ♦ Numeric value xxh, xxH xxb ♦ Unit word, W byte, B nibble, N maga-, M kilo-, K kilo-, k milli-, m micro-, µ nano-, n second, s (lower case) second ♦ Terminology “H” level, “1” level “L” ...
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... Pins ................................................................................................................................................................. 1-6 1.3.1 Pin Layout .............................................................................................................................................. 1-6 1.3.1.1 Pin Layout of ML610Q421 120pin TQFP Package .......................................................................... 1-6 1.3.1.2 Pin Layout of ML610Q422 120pin TQFP Package .......................................................................... 1-7 1.3.1.3 Pin Layout of ML610Q421 Chip ....................................................................................................... 1-8 1.3.1.4 Pin Layout of ML610Q422 Chip ....................................................................................................... 1-9 1.3.1.5 Pad Coordinates of ML610Q421 Chip ............................................................................................ 1-10 1 ...
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... Description of Operation................................................................................................................................ 6-6 6.3.1 Low-Speed Clock................................................................................................................................... 6-6 6.3.1.1 Low-Speed Clock Generation Circuit................................................................................................ 6-6 6.3.1.2 Operation of Low-Speed Clock Generation Circuit .......................................................................... 6-7 6.3.2 High-Speed Clock.................................................................................................................................. 6-8 6.3.2.1 500 kHz RC Oscillation ..................................................................................................................... 6-8 6.3.2.2 Crystal/Ceramic Oscillation Mode..................................................................................................... 6-9 ML610Q421/ML610Q422 User’s Manual Contents – 2 Contents ...
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... List of Registers ..................................................................................................................................... 9-2 9.2.2 1 kHz Timer Count Registers (T1KCRL, T1KCRH) ........................................................................... 9-3 9.2.3 1 kHz Timer Control Register (T1KCON) ........................................................................................... 9-4 9.3 Description of Operation................................................................................................................................ 9-5 Chapter 10 10. Timers............................................................................................................................................................... 10-1 10.1 Overview ...................................................................................................................................................... 10-1 10.1.1 Features ................................................................................................................................................ 10-1 10.1.2 Configuration ....................................................................................................................................... 10-1 ML610Q421/ML610Q422 User’s Manual Contents – 3 Contents ...
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... Watchdog Timer Control Register (WDTCON)................................................................................. 12-3 12.2.3 Watchdog Timer Mode Register (WDTMOD)................................................................................... 12-4 12.3 Description of Operation.............................................................................................................................. 12-5 12.3.1 Handling example when you do not want to use the watch dog timer............................................... 12-7 Chapter 13 13. Synchronous Serial Port................................................................................................................................... 13-1 13.1 Overview ...................................................................................................................................................... 13-1 ML610Q421/ML610Q422 User’s Manual Contents – 4 Contents ...
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... C Bus 0 Receive Register (I2C0RD) ................................................................................................ 15-3 2 15.2 Bus 0 Slave Address Register (I2C0SA) ...................................................................................... 15-4 2 15.2 Bus 0 Transmit Data Register (I2C0TD) ...................................................................................... 15-5 2 15.2 Bus 0 Control Register (I2C0CON).............................................................................................. 15-6 2 15.2 Bus 0 Mode Register (I2C0MOD)................................................................................................ 15-7 2 15.2 Bus 0 Status Register (I2C0STAT)............................................................................................... 15-8 ML610Q421/ML610Q422 User’s Manual Contents – 5 Contents ...
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... Description of Registers............................................................................................................................... 18-2 18.2.1 List of Registers ................................................................................................................................... 18-2 18.2.2 Port 1 Data Register (P1D) .................................................................................................................. 18-3 18.2.3 Port 1 Control Registers 0, 1 (P1CON0, P1CON1) ............................................................................ 18-4 18.3 Description of Operation.............................................................................................................................. 18-5 18.3.1 Input Port Function .............................................................................................................................. 18-5 18.3.2 Secondary Function ............................................................................................................................. 18-5 ML610Q421/ML610Q422 User’s Manual Contents – 6 Contents ...
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... Description of Operation............................................................................................................................ 21-11 21.3.1 Input/Output Port Functions .............................................................................................................. 21-11 21.3.2 Secondary and Tertiary Functions..................................................................................................... 21-11 Chapter 22 22. Port A ............................................................................................................................................................... 22-1 22.1 Overview ...................................................................................................................................................... 22-1 22.1.1 Features ................................................................................................................................................ 22-1 22.1.2 Configuration ....................................................................................................................................... 22-1 22.1.3 List of Pins ........................................................................................................................................... 22-1 22.2 Description of Registers............................................................................................................................... 22-2 ML610Q421/ML610Q422 User’s Manual Contents – 7 Contents ...
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... Functioning P35(RCM), P34(RCT0), P33(RT0), P32(RS0), P31(CS0) and P30(IN0) as the RC-ADC(Ch0) ................................................................................................................................... 24-21 24.4.2 Functioning P47(RT1), P46(RS1), P45(CS1) and P44(IN1) as the RC-ADC(Ch1) ....................... 24-22 Chapter 25 25. Successive Approximation Type A/D Converter............................................................................................ 25-1 25.1 Overview ...................................................................................................................................................... 25-1 25.1.1 Features ................................................................................................................................................ 25-1 25.1.2 Configuration ....................................................................................................................................... 25-1 ML610Q421/ML610Q422 User’s Manual Contents – 8 Contents ...
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... Description of Operation.............................................................................................................................. 27-5 27.3.1 Threshold Voltage................................................................................................................................ 27-5 27.3.2 Operation of Battery Level Detector ................................................................................................... 27-6 Chapter 28 28. Power Supply Circuit ....................................................................................................................................... 28-1 28.1 Overview ...................................................................................................................................................... 28-1 28.1.1 Features ................................................................................................................................................ 28-1 28.1.2 Configuration ....................................................................................................................................... 28-1 28.1.3 List of Pins ........................................................................................................................................... 28-1 28.2 Description of Operation.............................................................................................................................. 28-2 ML610Q421/ML610Q422 User’s Manual Contents – 9 Contents ...
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... Method of Connecting to On-Chip Debug Emulator.................................................................................. 29-1 29.3 Flash Memory Rewrite Function ................................................................................................................. 29-2 Appendixes Appendix A Registers ............................................................................................................................................ A-1 Appendix B Package Dimensions ..........................................................................................................................B-1 Appendix C Electrical Characteristics....................................................................................................................C-1 Appendix D Application Circuit Example ............................................................................................................ D-1 Appendix E Check List ...........................................................................................................................................E-1 Revision History Revision History.........................................................................................................................................................R-1 ML610Q421/ML610Q422 User’s Manual Contents – 10 Contents ...
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Chapter 1 Overview ...
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... Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) • Timers − 8 bits × 4 channels (Timer0-3: 16-bit x 2 configuration available by using Timer0-1 or Timer2-3) − Clock frequency measurement mode (in one channel of 16-bit configuration using Timer2-3) • 1 kHz timer − 10 Hz/1 Hz interrupt function ML610Q421/ML610Q422 User’s Manual 1 – 1 Chapter 1 Overview ...
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... Non-maskable interrupt input port × 1 channel − Input-only port × 6 channels (including secondary functions) − Output-only port × 3 channels (including secondary functions) − Input/output port ML610Q421: 22 channels (including secondary functions) ML610Q422: 14 channels (including secondary functions) ML610Q421/ML610Q422 User’s Manual 1 – 2 Chapter 1 Overview ...
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... Dot matrix can be supported. ML610Q421: 400 dots max. (50 seg × 8 com), 1/1 to 1/8 duty ML610Q422: 800 dots max. (50 seg × 16 com), 1/1 to 1/16 duty − 1/3 or 1/4 bias (built-in bias generation circuit) − Frame frequency selecable (approx. 64 Hz, 73 Hz, 85 Hz, and 102 Hz) − ...
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... ML610Q422B-xxxWA (Blank product: ML610Q422B-NNNWA) − 120-pin plastic TQFP ML610Q421-xxxTBZ03A (Blank product: ML610Q421-NNNTBZ03A) ML610Q422-xxxTBZ03A (Blank product: ML610Q422-NNNTBZ03A) ML610Q421P-xxxTBZ03A (Blank product: ML610Q421P-NNNTBZ03A) ML610Q422P-xxxTBZ03A (Blank product: ML610Q422P-NNNTBZ03A) ML610Q421B-xxxTBZ03A (Blank product: ML610Q421B-NNNTBZ03A) ML610Q422B-xxxTBZ03A (Blank product: ML610Q422B-NNNTBZ03A) xxx: ROM code number P: Wide range temperature version B: Low-speed clock oscillation stop detection reset un-carrying version • ...
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... IN1* CS1* RS1* RT1 INT REF 12bit-ADC AIN0, AIN1 BLD * Secondary function or Tertiary function Figure 1-1 Block Diagram of ML610Q421 ML610Q421/ML610Q422 User’s Manual CPU (nX-U8/100) ELR1～3 ECSR1～3 GREG 0～15 LR DSR/CSR EA PC ALU SP BUS Controller Instruction Register Data-bus INT RAM ...
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... RCM* ×2 IN1* CS1* RS1* RT1 INT REF 12bit-ADC AIN0, AIN1 BLD * Secondary function or Tertiary function Figure 1-2 Block Diagram of ML610Q422 ML610Q421/ML610Q422 User’s Manual CPU (nX-U8/100) ELR1～3 ECSR1～3 LR DSR/CSR EA PC ALU SP BUS Instruction Controller Register Data-bus INT 1 RAM ...
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... AIN0 118 AIN1 119 AVDD 120 120pin 1pin (NC): No Connection Note: The assignment of the pads P30 to P35 are not in order. Figure 1-3 Pin Layout of ML610Q421 Package ML610Q421/ML610Q422 User’s Manual 1 – 7 Chapter 1 Overview 61pin 60pin SEG18 60 SEG17 59 SEG16 58 SEG15 57 SEG14 ...
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... VREF 117 AIN0 118 AIN1 119 AVDD 120 120pin 1pin (NC): No Connection Note: The assignment of the pads P30 to P35 are not in order. Figure 1-4 Pin Layout of ML610Q422 Package ML610Q421/ML610Q422 User’s Manual 1 – 8 Chapter 1 Overview 61pin 60pin SEG18 60 SEG17 59 SEG16 58 SEG15 ...
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... AIN1 115 AVDD 116 Note: The assignment of the pads P30 to P35 are not in order. Figure 1-5 Dimensions of ML610Q421 Chip ML610Q421/ML610Q422 User’s Manual 2.98mm 2.98 mm × 3.02mm Chip size: PAD count: 116 pins 80 μm Minimum PAD pitch: 70 μm ×70 μm PAD aperture: 350 μ ...
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... AIN0 114 AIN1 115 AVDD 116 Note: The assignment of the pads P30 to P35 are not in order. Figure 1-6 Dimensions of ML610Q422 Chip ML610Q421/ML610Q422 User’s Manual 2.98mm 2.98 mm × 3.02 mm Chip size: PAD count: 116 pins 80 μm Minimum PAD pitch: 70 μm × 70 μm PAD aperture: 350 μ ...
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... SEG5 1384 160 46 SEG6 1384 240 47 SEG7 1384 320 48 SEG8 1384 400 49 SEG9 1384 480 50 SEG10 1384 560 ML610Q421/ML610Q422 User’s Manual PAD Pad X Y No. Name (μm) (μm) 51 SEG11 1384 640 52 SEG12 1384 720 53 SEG13 1384 800 54 SEG14 1384 880 ...
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... Pad Coordinates of ML610Q422 Chip Table 1-2 Pad Coordinates of ML610Q422 PAD Pad X Y No. Name (μm) (μm) 1 VPP -1240 -1404 2 RESET_N -1160 -1404 3 P42 -1080 -1404 4 P43 -1000 -1404 5 P44 -920 -1404 6 P45 -840 -1404 7 P46 -760 -1404 8 P47 -680 -1404 9 P30 ...
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... Low-speed clock 21 21 XT1 O oscillation pin Reference power supply pin for ⎯ successive 113 113 V REF approximation type ADC ML610Q421/ML610Q422 User’s Manual Secondary function Pin name I/O Function ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ...
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... I/O P1CK external clock input I/O Input/output port 7 7 P46 I/O Input/output port 8 8 P47 Input/output port ⎯ 98 PA0 I/O ML610Q421/ML610Q422 User’s Manual Secondary function Pin name I/O Function ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ...
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... SEG22 O LCD segment pin 63 63 SEG23 SEG24 O LCD segment pin LCD segment pin 65 65 SEG25 O ML610Q421/ML610Q422 User’s Manual Secondary function Pin name I/O Function ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ...
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... SEG46 O LCD segment pin 87 87 SEG47 O LCD segment pin 88 88 SEG48 O LCD segment pin 89 89 SEG49 O ML610Q421/ML610Q422 User’s Manual Secondary function Pin name I/O Function ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ...
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... Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. I/O General-purpose input/output port. PA0-PA7 These pins are for the ML610Q421, but are not provided in the ML610Q422. ML610Q421/ML610Q422 User’s Manual Description 1 – 17 Chapter 1 Overview Primary/ Secondary/ ...
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... Melody Melody/buzzer signal output pin. This pin is used as the secondary MD0 O function of the P22 pin. LED drive Nch open drain output pins to drive LED. LED0-2 O ML610Q421/ML610Q422 User’s Manual Description C, externally connect a pull-up resistor. 1 – 18 Chapter 1 Overview Primary/ Secondary/ Logic Tertiary ...
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... LCD drive signal Common output pins. COM0-7 O Common output pins. COM8-15 O These pins are for the ML610Q422, but are not provided in the ML610Q421. Segment output pin. SEG0-49 O LCD driver power supply Power supply pins for LCD bias (internally generated). Capacitors Ca, Cb, V — ...
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... DDX Capacitor Cx (see measuring circuit 1) is connected between this pin and Power supply pin for programming Flash ROM. A pull-up resistor is V — PP internally connected. ML610Q421/ML610Q422 User’s Manual Description 1 – 20 Chapter 1 Overview Primary/ Secondary/ Logic Tertiary — — — — ...
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... It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting. Table 1-3 Termination of Unused Pins Recommended pin termination 1 – 21 ML610Q421/ML610Q422 User’s Manual Chapter 1 Overview Open ...
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CPU and Memory Space Chapter 2 ...
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... Segment0 Vector Table Area or Program Code ROM Window Area Program Code or ROM Window Area Test Data Area 8bit 2 – 1 ML610Q421/ML610Q422 User’s Manual Chapter 2 CPU and Memory Space 0:7C00H T est Data Area Write-able 0:7DFFH 0:7E00H T est Data Area Non write-able 0:7FFFH ...
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... The contents of Segment 0 of the program memory space is read from the ROM reference area of Segment 8. 2.4 Instruction Length The length of a instruction is 16 bits. 2.5 Data Type The data types supported include byte (8 bits) and word (16 bits). ML610Q421/ML610Q422 User’s Manual Segment 0 DSR: Data address ROM Window Area Unused Area RAM Area ...
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... Description of Registers 2.6.1 List of Registers Address Name 0F000H Data segment register ML610Q421/ML610Q422 User’s Manual Chapter 2 CPU and Memory Space Symbol (Byte) Symbol (Word) ⎯ DSR 2 – 3 R/W Size Initial value R/W 8 00H ...
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... Manual”. [Description of Bits] • DSR3-DSR0 (bits 3-0) DSR3 DSR2 DSR1 ML610Q421/ML610Q422 User’s Manual Chapter 2 CPU and Memory Space ⎯ ⎯ DSR3 DSR2 R/W R/W R DSR0 0 Data segment 0 (initial value Prohibited Data segment Prohibited – DSR1 DSR0 R/W R/W R Description ...
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Chapter 3 Reset Function ...
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... Low-speed Oscillation stop detect reset WDT reset RSTAT: Reset status register Figure 3-1 Configuration of Reset Generation Circuit 3.1.3 List of Pin Pin name I/O Reset input pin RESET_N I ML610Q421/ML610Q422 User’s Manual Chapter 3 Reset Function Reset signal RST AT Data bus Description 3 – 1 ...
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... The WSDTR is a flag that indicates that the watchdog timer reset is generated. This bit is set to “1” when the reset by overflow of the watchdog timer is generated. WDTR Watchdog timer reset not occurred 0 Watchdog timer reset occurred 1 Note: No flag is provided that indicates the occurrence of reset by the RESET_N pin. ML610Q421/ML610Q422 User’s Manual Symbol (Byte) Symbol (Word) ⎯ RST ― ...
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... In system reset mode, the contents of data memory and those of any SFR whose initial value is undefined are not initialized and are undefined. Initialize them by software. In system reset mode by the BRK instruction, no special function register (SFR) that has a fixed initial value is initialized either. Therefore initialize such an SFR by software. ML610Q421/ML610Q422 User’s Manual Chapter 3 Reset Function 3 – 3 ...
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MCU Control Function Chapter 4 ...
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... Configuration Figure 4-1 shows an operating state transition diagram. Power on System reset mode Reset STOP mode Figure 4-1 Operating State Transition Diagram ML610Q421/ML610Q422 User’s Manual Chapter 4 MCU Control Function Release of reset Program run mode Reset or BRK instruction “1” Reset HLT = “ ...
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... Block control register 0 0F028H Block control register 1 0F029H Block control register 2 0F02AH Block control register 3 0F02BH Block control register 4 0F02CH ML610Q421/ML610Q422 User’s Manual Chapter 4 MCU Control Function Symbol (Byte) Symbol (Word) ⎯ STPACP ⎯ SBYCON BLKCON0 ⎯ ⎯ BLKCON1 ⎯ ...
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... During a system reset, the stop code acceptor is disabled. Note: The STOP code acceptor can not be enabled on the condition of that both any interrupt enable flag and the corresponding interrupt request flag are “1”(An interrupt request occurrence with resetting MIE flag will have the condition). ML610Q421/ML610Q422 User’s Manual ― ...
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... When a maskable interrupt source (interrupt with enable bit) occurs while the MIE flag of the program status word (PSW) in the nX-U8/100 core is “0”, the STOP mode and the HALT mode are simply released and interrupt processing is not performed. Refer to the “nX-U8/100 Core Instruction Manual” for details of PSW. ML610Q421/ML610Q422 User’s Manual ― ...
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... Ensure the bits are reset to “0” before using the peripherals to enable the operation. See Chapter 10, “Timers” for detail about operation of Timer 0, Timer 1, Timer 2 and Timer 3. ML610Q421/ML610Q422 User’s Manual ― ...
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... See Chapter 8, “Capture” for detail about operation of Capture. See Chapter 9, “1kHz Timer” for detail about operation of 1kHz Timer. See Chapter 11, “PWM” for detail about operation of PWM. ML610Q421/ML610Q422 User’s Manual ― ...
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... See Chapter 15, “I2C Bus Interface” for detail about operation of I2C Bus Interface. See Chapter 14, “UART” for detail about operation of UART. See Chapter 13, “Synchronous Serial Port” for detail about operation of SSIO. ML610Q421/ML610Q422 User’s Manual ― ...
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... Ensure the bits are reset to “0” before using the peripherals to enable the operation. See Chapter 23, “Melody Driver” for detail about operation of Melody/Buzzer. ML610Q421/ML610Q422 User’s Manual ― ...
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... The DRAD bit is used to control RC type A/D converter operation. When the DRAD bit is set to “1”, the circuits related to RC type A/D converter are reset and turned off. DRAD Enable operating RC type A/D converter (initial value) 0 Disable operating RC type A/D converter 1 ML610Q421/ML610Q422 User’s Manual DBLD DXTSP ― ...
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... See Chapter 3, “Reset Function” for detail about operation of 32kHz oscillation stop detector. See Chapter 24, “RC Oscillation Type A/D Converter” for detail about operation of RC oscillation type A/D converter. See Chapter 25, “Successive Approximation” for detail about operation of SA type A/D converter. ML610Q421/ML610Q422 User’s Manual Chapter 4 MCU Control Function Description ...
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... Since up to two instructions are executed during the period between HALT mode release and a transition to interrupt processing, place two NOP instructions next to the instruction that sets the HLT bit to “1”. ML610Q421/ML610Q422 User’s Manual Chapter 4 MCU Control Function HALT mode Program operating mode 4 – ...
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... Oscillation waveform waveform HSCLK HSCLK waveform SBYCON.STP bit Interrupt request Program operating mode Figure 4-3 Operation Waveforms in STOP Mode When CPU Operates with Low-Speed Clock ML610Q421/ML610Q422 User’s Manual Chapter 4 MCU Control Function Oscillation waveform Hiz Low-speed oscillation T 8192-pulse count XTL ...
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... The STOP mode is entered two cycles after the instruction that sets the STP bit to “1” and up to two instructions are executed during the period between STOP mode release and a transition to interrupt processing. Therefore, place two NOP instructions next to the instruction that set the STP bit to “1”. ML610Q421/ML610Q422 User’s Manual Chapter 4 MCU Control Function High-speed oscillation waveform ...
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... STP/HLT bit to “1” program operation does not go to the 1 interrupt routine. After the mode is returned from the STOP/HALT mode, program operation restarts from the instruction following the instruction that 1 sets the STP/HLT bit to “1”, then goes to the interrupt routine. 4 – 14 ML610Q421/ML610Q422 User’s Manual Chapter 4 MCU Control Function ...
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... RC type A/D converter and SAR type A/D converter. Note: DXTSP bit (bit 4) of BLKCON4 register disables the operation of 32kHz oscillation stop detector in HALT mode only. See the each chapter for detail about the opeation of each peripheral and relevant notes. ML610Q421/ML610Q422 User’s Manual Chapter 4 MCU Control Function 4 – 15 ...
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Chapter 5 Interrupts (INTs) ...
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... Features • 2 non-maskable interrupt sources (Internal source: 1, External source: 1) • 20 maskable interrupt sources (Internal sources: 16, External sources: 4) • Software interrupt (SWI): 64 sources max. • External interrupts allow edge selection and sampling selection. ML610Q421/ML610Q422 User’s Manual Chapter 5 Interrupts (INTs) 5 – 1 ...
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... Interrupt request register 2 0F01BH Interrupt request register 3 0F01CH Interrupt request register 4 0F01DH Interrupt request register 5 0F01EH Interrupt request register 6 0F01FH Interrupt request register 7 ML610Q421/ML610Q422 User’s Manual Chapter 5 Interrupts (INTs) Symbol (Byte) Symbol (Word) R/W ⎯ IE1 R/W ⎯ IE2 R/W ⎯ ...
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... EP02 is the enable flag for the input port P02 pin interrupt (P02INT). EP02 0 Disabled (initial value) 1 Enabled • EP03 (bit 3) EP03 is the enable flag for the input port P03 pin interrupt (P03INT). EP03 0 Disabled (initial value) 1 Enabled ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ EP03 EP02 R/W R/W R ...
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... ESAD is the enable flag for the successive approximation type A/D converter interrupt (SADINT). ESAD 0 Disabled (initial value) 1 Enabled • EI2C0 (bit 7) EI2C0 is the enable flag for the I2C bus 0 interrupt (I2C0INT). EI2C0 0 Disabled (initial value) 1 Enabled ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ ⎯ ESAD R/W R/W R ...
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... ETM0 is the enable flag for the timer 0 interrupt (TM0INT). ETM0 0 Disabled (initial value) 1 Enabled • ETM1 (bit 1) ETM1 is the enable flag for the timer 1 interrupt (TM1INT). ETM1 0 Disabled (initial value) 1 Enabled ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ ⎯ R/W R/W R Description Description 5 – ...
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... EMD0 is the enable flag for the melody 0 interrupt (MD0INT). EMD0 0 Disabled (initial value) 1 Enabled • ERAD (bit 5) ERAD is the enable flag for the RC oscillation type A/D converter interrupt (RADINT). ERAD 0 Disabled (initial value) 1 Enabled ML610Q421/ML610Q422 User’s Manual ERAD ⎯ ⎯ EMD0 R/W R/W R ...
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... ETM2 the enable flag for the timer 2 interrupt (TM2INT). ETM2 0 Disabled (initial value) 1 Enabled • ETM3 (bit 5) ETM3 the enable flag for the timer 3 interrupt (TM3INT) ETM3 0 Disabled (initial value) 1 Enabled ML610Q421/ML610Q422 User’s Manual ETM3 ETM2 ⎯ R/W R/W R Description Description 5 – ...
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... E128H is the enable flag for the time base counter 128 Hz interrupt (T128HINT). E128H 0 Disabled (initial value) 1 Enabled • E32H (bit 7) E32H is the enable flag for the time base counter 32 Hz interrupt (T32HINT). E32H 0 Disabled (initial value) 1 Enabled ML610Q421/ML610Q422 User’s Manual E128H ET1K ⎯ R/W R/W R ...
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... E16H is the enable flag for the time base counter 16 Hz interrupt (T16HINT). E16H 0 Disabled (initial value) 1 Enabled • E2H (bit 3) E2H is the enable flag for the time base counter 2 Hz interrupt (T2HINT). E2H 0 Disabled (initial value) 1 Enabled ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ E2H R/W R/W R ...
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... QNMI is the request flag for the NMI interrupt (NMINT). QNMI 0 No request (initial value) 1 Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ0), the interrupt shift cycle starts after the next 1 instruction is executed. ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ ⎯ R/W R/W ...
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... QP03 0 No request (initial value) 1 Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ1 the interrupt enable register (IE1), the interrupt shift cycle starts after the next 1 instruction is executed. ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ QP03 QP02 ...
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... QI2C0 0 No request (initial value) 1 Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ2 the interrupt enable register (IE2), the interrupt shift cycle starts after the next 1 instruction is executed. ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ ⎯ QSAD ...
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... QTM1 0 No request (initial value) 1 Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ3 the interrupt enable register (IE3), the interrupt shift cycle starts after the next 1 instruction is executed. ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ ⎯ R/W ...
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... QRAD 0 No request (initial value) 1 Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ4 the interrupt enable register (IE4), the interrupt shift cycle starts after the next 1 instruction is executed. ML610Q421/ML610Q422 User’s Manual QRAD ⎯ ⎯ QMD0 ...
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... QTM3 0 No request (initial value) 1 Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ5 the interrupt enable register (IE5), the interrupt shift cycle starts after the next 1 instruction is executed. ML610Q421/ML610Q422 User’s Manual QTM2 ⎯ ⎯ R/W ...
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... Q32H 0 No request (initial value) 1 Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ6 the interrupt enable register (IE6), the interrupt shift cycle starts after the next 1 instruction is executed. ML610Q421/ML610Q422 User’s Manual Q128H QT1K ⎯ R/W ...
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... No request (initial value) 1 Request Note: When an interrupt is generated by the instruction to write to the interrupt request register (IRQ7 the interrupt enable register (IE7), the the interrupt shift cycle starts after the next 1 instruction is executed. ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ Q2H R/W ...
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... When multiple interrupts are generated concurrently, the interrupts are serviced according to this priority and processing of low-priority interrupts is pending. - Please define vector tables for all unused interrupts for fail safe. ML610Q421/ML610Q422 User’s Manual Table 5-1 Interrupt Sources Interrupt source Symbol WDT INT ...
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... Set the MIE flag to “0”. (5) Set the ELEVEL field to “1”. (6) Load the interrupt start address into PC. Reference: For the MIE flag, Program Counter (PC), CSR, PSW, and ELEVEL, see “nX-U8/100 Core Instruction Manual”. ML610Q421/ML610Q422 User’s Manual Chapter 5 Interrupts (INTs) 5 – 19 ...
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... Example of description: State A-1-1 Intrpt_A-1-1: ; A-1-1 state DI ; Disable interrupt : : : RTI ; Return PC from ELR ; Return PSW form EPSW ; End ML610Q421/ML610Q422 User’s Manual Chapter 5 Interrupts (INTs) Example of description: State A-1-2 Intrpt_A-1-2: ; Start ; Save ELR and EPSW at the PUSH ELR, EPSW beginning EI ; Enable interrupt : : ...
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... PUSH ELR, EPSW, the beginning Enable interrupt : : : BL Sub_1 ; Call subroutine Sub_1 : POP PC, PSW Return PC from the stack ; Return PSW from the stack ; Return LR from the stack ; End ML610Q421/ML610Q422 User’s Manual Chapter 5 Interrupts (INTs) Sub_1 Disable interrupt : : : RT ; Return PC from LR ; End of subroutine 5 – 21 ...
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... BL Sub_1 ; Call subroutine Sub_1 : POP PC，PSW，LR ; Return PC from the stack ; Return PSW from the stack ; Return LR from the stack ; End ML610Q421/ML610Q422 User’s Manual Chapter 5 Interrupts (INTs) Example of description: B-2-1 Intrpt_B-2-1: ; Start PUSH ELR，EPSW ; Save ELR, EPSW at the beginning ...
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... Between the DSR prefix instruction and the next instruction When the interrupt conditions are satisfied in this section, an interrupt is generated immediately after execution of the instruction following the DSR prefix instruction. Reference: For the DSR prefix instruction, see “nX-U8/100 Core Instruction Manual”. ML610Q421/ML610Q422 User’s Manual Chapter 5 Interrupts (INTs) 5 – 23 ...
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Clock Generation Circuit Chapter 6 ...
Page 87
... This LSI starts operation with a clock generated by dividing the 500 kHz RC oscillation frequency by 8 after power- system reset. At initialization by software, set the FCON0 or FCON1 register to switch the clock to a required one. Operation of this LSI is not guaranteed under a condition where a low-speed clock is not supplied. ML610Q421/ML610Q422 User’s Manual Chapter 6 Clock Generation Circuit Divide ratio ...
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... Used for the secondary function of the P11 pin 6.2 Description of Registers 6.2.1 List of Registers Address Name Frequency control register 0 0F002H Frequency control register 1 0F003H ML610Q421/ML610Q422 User’s Manual Chapter 6 Clock Generation Circuit Description Symbol (Byte) Symbol (Word) FCON0 FCON FCON1 6 – 2 Initial R/W ...
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... OSCLK, 1/2OSCLK, 1/4OSCLK, or 1/8OSCLK can be selected. At system reset, 1/8OSCLK is selected. OUTC1 OUT C0 OSCLK 0 0 1/2OSCLK 0 1 1/4OSCLK 1 0 1/8OSCLK (initial value ML610Q421/ML610Q422 User’s Manual OUT C1 OUT C0 OSCM1 R/W R/W R Description Description Description 6 – 3 Chapter 6 Clock Generation Circuit ...
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... When built-in PLL (about 8.192 MHz) oscillation mode is selected (OSCM1 = “1”, OSCM0 = “0”), 1/2OSCLK (about 4.096 MHz) is output as HSCLK even if OSCLK (SYSC0 = “0”, SYSC1 = “1”) is selected. ML610Q421/ML610Q422 User’s Manual Chapter 6 Clock Generation Circuit 6 – 4 ...
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... When the LPLL bit is set to “0”, this indicates that the PLL oscillation is inactive or the PLL oscillation frequency is not within 8.192 MHz±2.5%. LPLL is a read-only bit. LPLL Disables the use of PLL oscillation (initial value) 0 Enables the use of PLL oscillation 1 ML610Q421/ML610Q422 User’s Manual Chapter 6 Clock Generation Circuit ⎯ ⎯ ⎯ ...
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... Notes: − Install a crystal as close to the LSI as possible and make sure that signals causing noise and power supply wiring are not near the crystal and its wiring. − Note that oscillation may stop due to condensation. ML610Q421/ML610Q422 User’s Manual and required. GL ...
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... Low-speed oscillation Count: 8192 LSCLK waveform Start of LSCLK STOP supply mode Occurrence of external interrupt 6 – 7 ML610Q421/ML610Q422 User’s Manual Chapter 6 Clock Generation Circuit T : Oscillation start time X TL Low-speed clock oscillation waveform Low-speed oscillation Count: 4096 Low-speed oscillation Count: 8192 LSCLK waveform ...
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... The RC oscillation mode is allowed within the range of V − After system reset mode is released, supply of OSCLK starts after the RC oscillation clock pulse count reaches 8192. After release of a STOP mode, supply of OSCLK starts. ML610Q421/ML610Q422 User’s Manual Chapter 6 Clock Generation Circuit ST OP mode ...
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... Note that oscillation may stop due to condensation. − The crystal or the ceramic resonator connected to the P10/OSC0 and P11/OSC1 pins should not exceed the guaranteed maximum operation frequency of 4.2 MHz of the system clock (SYSCLK) of this LSI. ML610Q421/ML610Q422 User’s Manual V DD ...
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... DD − The clock that is input should not exceed the guaranteed maximum operating frequency 4.2 MHz of the system clock (SYSCLK) of this LSI. ML610Q421/ML610Q422 User’s Manual V DDL STOP mode PLL oscillation ENOSC (Enables oscillation) ...
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... The oscillation stabilization period is the duration of 128 clock pulses in 500 kHz RC oscillation mode and external clock input mode and the duration of 4096 clock pulses in the crystal/ceramic oscillation mode and PLL oscillation mode. ML610Q421/ML610Q422 User’s Manual Oscillation start time ...
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... High-speed/PLL oscillation start time XTH PLL High-speed oscillation waveform HSCLK waveform Low-speed clock oscillation waveform STOP mode Generation of external 6 – 12 ML610Q421/ML610Q422 User’s Manual Chapter 6 Clock Generation Circuit High-speed/PLL oscillation start time XTH PLL High-speed oscillation waveform High-speed oscillation Count: 4096 ...
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... STOP mode, the CPU becomes inactive until LSCLK starts clock supply to the peripheral circuits. Therefore recommended to switch to LSCLK after confirming that the LSCLK is oscillating by checking that the time base counter interrupt request bit (Q128H) is “1”. ML610Q421/ML610Q422 User’s Manual Chapter 6 Clock Generation Circuit System clock switching (High-speed clock→Low-speed clock) ...
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... If the system clock is switched from a low-speed clock to a high-speed clock before the high-speed clock (HSCLK) starts oscillation, the CPU becomes inactive until HSCLK starts clock supply to the peripheral circuits. ML610Q421/ML610Q422 User’s Manual Set high-speed oscillation mode before switching the system clock. ...
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... Bit does not exist Bit not related to the high speed clock function ** : Don’t care the data. Note: P21(Port2 output-only port, does not have an register to select the data direction(input or output). ML610Q421/ML610Q422 User’s Manual Chapter 6 Clock Generation Circuit P2MOD register (Address: 0F214H ...
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... Bit does not exist Bit not related to the low speed clock function ** : Don’t care the data. Note: P20(Port2 output-only port, does not have an register to select the data direction(i.e. input or output). ML610Q421/ML610Q422 User’s Manual Chapter 6 Clock Generation Circuit P2MOD register (Address: 0F214H ...
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Time Base Counter Chapter 7 ...
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... LTBR : Low-speed time base counter register LTBADJL : Low-speed time base counter frequency adjust register LTBADJH : Low-speed time base counter frequency adjust register Figure 7-1 Configuration of Low-Speed Time Base Counter (LTBC) ML610Q421/ML610Q422 User’s Manual LTBR 8-bit Counter – 1 Chapter 7 Time Base Counter ...
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... HTBDR: High-speed time base counter frequency divide register Figure 7-2 Configuration of High-Speed Time Base Counter Note: The frequency of HSCLK changes according to specified data in SYSC1 bit and SYSC0 bit of Frequency control register 0 (FON0) ML610Q421/ML610Q422 User’s Manual Chapter 7 Time Base Counter HT BDR HTBCLK 1/n-Counter 4 ...
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... High-speed time base counter 0F00BH frequency divide register Low-speed time base counter 0F00CH frequency adjustment register L Low-speed time base counter 0F00DH frequency adjustment register H ML610Q421/ML610Q422 User’s Manual Chapter 7 Time Base Counter Symbol (Byte) Symbol (Word) R/W ⎯ LTBR R/W ⎯ ...
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... The T128HZ-T1HZ outputs are set to “0” when write operation is performed for LTBR. Note: A TBC interrupt (128Hz interrupt, 32Hz interrupt, 16Hz interrupt, or 2Hz interrupt) may occur depending on the LTBR write timing (see Figure 7-4, “Interrupt Timing and Reset Timing by Writing to LTBR”). Therefore, take care in software programming. ML610Q421/ML610Q422 User’s Manual T4HZ ...
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... Indicates the frequency when the high-speed oscillation clock, HSCLK, is 4096 kHz. ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ HTD3 R/W R/W R Divide ratio × 1/16 (initial value) 0 × 1/15 1 × 1/14 0 × 1/13 1 × 1/12 0 × 1/11 1 × 1/10 0 × 1/9 1 × 1/8 0 × ...
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... The LADJS and LADJ9 to LADJ0 bits are used to adjust frequency. Approx. −488ppm to +488ppm. Adjustment range: Adjustment accuracy: Approx. 0.48ppm See Section 7.3.3, “Low-Speed Time Base Counter Frequency Adjustment Function” for the correspondence between the frequency adjustment values (LTBADJH, LTBADJL) and adjustment ratio. ML610Q421/ML610Q422 User’s Manual LADJ5 LADJ4 LADJ3 ...
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... T128HZ T64HZ T32HZ T16HZ T16HZ T8HZ T4HZ T2HZ T1HZ Figure 7-4 Interrupt Timing and Reset Timing by Writing to LTBR ML610Q421/ML610Q422 User’s Manual ; EA←LTBR address [EA] ; 1st read [EA] ; 2nd read R1 ; Comparison for LTBR ; To MARK when the values do not coincide 7 – 7 Chapter 7 Time Base Counter ...
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... Figure 7-5 shows the output waveform of HTBCLK. High-speed clock HSCLK 1/n counter output HTBCLK High-speed time base counter Divide register HTBDR Figure 7-5 Output Waveform of HTBCLK ML610Q421/ML610Q422 User’s Manual × 1/1 × 1/2 0FH 0EH 7 – 8 Chapter 7 Time Base Counter × 1/3 0DH ...
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... The low-speed clock (LSCLK) and the outputs of T32KHZ and T16KHZ of LTBC are not adjusted by the frequency adjust function. The frequency adjustment accuracy does not guarantee the accuracy including the frequency variation of the crystal oscillation (32.768kHz) due to temperature variations. ML610Q421/ML610Q422 User’s Manual Hexadecimal Frequency adjustment ratio (ppm ...
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... A signal (437C) used for 16bit timer 2-3 frequency measurement mode is generated in the time base conter block. See Chapter 10, “Timer” for more detail about the frequency measurement function. LSCLK Figure 7-6 437c signal generation block diagram (used for frequency measurement mode) ML610Q421/ML610Q422 User’s Manual 16KHz 8KHz 4KHz ...
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Chapter 8 Capture ...
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... List of Pins Pin name I/O Capture 0 input pin P00/CAP0 I Used as the secondary function of the P00 pin. Capture 1 input pin P01/CAP1 I Used as the secondary function of the P01 pin. ML610Q421/ML610Q422 User’s Manual Capture CAPR1 Controller CAPSTAT CP1F CP0F Description 8 – 1 Chapter 8 Capture ...
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... Description of Registers 8.2.1 List of Registers Address Name 0F090H Capture control register 0F091H Capture status register 0F092H Capture data register 0 0F093H Capture data register 1 ML610Q421/ML610Q422 User’s Manual Symbol (Byte) Symbol (Word) R/W ⎯ CAPCON R/W ⎯ CAPSTAT R/W ⎯ CAPR0 R/W ⎯ ...
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... Stops the capture 0 operation. (initial value) 1 Starts the capture 0 operation. • ECAP1 (bit 1) The ECAP1 bit is used to start or stop the operation of capture 1. ECAP1 0 Stops the capture 1 operation. (initial value) 1 Starts the capture 1 operation. ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ ⎯ R/W R/W R/W ...
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... When the CAPF0 bit is set to "1", it indicates that data is captured in capture data register 0 (CAPR1). When the CAPF1 bit is set to "1", the next capture operation is stopped. So perform the write operation to capture data register 1 (CAPR1) to clear theCAPF0 bit to "0". CAPF1 0 No capture 1 latch (initial value) 1 Capture 1 latch ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ ⎯ R/W ...
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... The T4KHZ to T32HZ signals of the low-speed time base counter (LTBC) are captured when the P00 interrupt request is generated with the CAPF0 flag (bit 0 of the CAPSTAT register) set to "0". Writing to CAPR0 sets the CAPF0 flag of CAPSTAT to "0". The value of CAPR0 does not change even if data is written to it. ML610Q421/ML610Q422 User’s Manual ...
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... The T4KHZ to T32HZ signals of the low-speed time base counter (LTBC) are captured when the P01 interrupt request is generated with the CAPF1 flag (bit 1 of the CAPSTAT register) set to "0". Writing to CAPR1 sets the CAPF1 flag of CAPSTAT to "0". The value of CAPR1 does not change even if data is written to it. ML610Q421/ML610Q422 User’s Manual ...
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... Figure 8-2 Timing Diagram of Capture Operation Note: When CPU is operating at the high speed (HSCLK), check that the capture flag (CAPF0, CAPF1) is set to "1" after the P00 or P01 interrupt request is generated and then read capture data register (CAPR0, CAPR1). ML610Q421/ML610Q422 User’s Manual N+1 XX N+1 8 – ...
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Timer (1kHzTM) Chapter 9 ...
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... Data bus T1KCON : 1 kHz timer control register T1KCRL : 1 kHz timer count register L T1KCRH : 1 kHz timer count register H Figure 9-1 Configuration of 1 kHz Timer ML610Q421/ML610Q422 User’s Manual Chapter 9 1 kHz Timer (1kHzTM) Interrupt control 1 kHz signal 10 Hz Binary/ternary T1KCRL counter Decimal×1 digit Decimal× ...
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... Description of Registers 9.2.1 List of Registers Address Name 0F080H 1 kHz timer count register L 0F081H 1 kHz timer count register H 0F082H 1 kHz timer control register ML610Q421/ML610Q422 User’s Manual Chapter 9 1 kHz Timer (1kHzTM) Symbol (Byte) Symbol (Word) R/W T1KCRL R/W T1KCR T 1KCRH R/W ⎯ ...
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... T1KCRL and T1KCRH are special function registers (SFRs) to read the decimal count values of the 1 kHz timer. When the write operation to T1KCRL or T1KCRH, the valid bit of T1KCRL or T1KCRH is "0" respectively. [Description of Bits] • T1KC11 to T1KC0 (T1KCRH: bits T1KCRL: bits T1KC11 to T1KC0 indicate the count values of the 1 kHz timer. ML610Q421/ML610Q422 User’s Manual T1KC1 T1KC0 ⎯ ...
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... Stops 1 kHz timer operation (initial value). 1 Starts 1 kHz operation. • T1KSEL (bit 1) The T1LSEL bit is used to select the interrupt period of the 1 kHz timer. The interrupt can be selected. T1KSEL interrupt (initial value interrupt ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ ⎯ R/W R/W R/W ...
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... LEA offset T1KCRL ; EA←T1KCRL address MARK: L ER0, [EA] L ER2, [EA] ; CMP ER0, ER1 BNE MARK ; : Figure 9-2 Example of Program for Reading T1KCRL and T1KCRH ML610Q421/ML610Q422 User’s Manual Chapter 9 1 kHz Timer (1kHzTM) ; First read ; Second read ; Comparison of T1KCRL and T1CKRH ; To MARK when not matched. 9 – 5 ...
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Chapter 10 Timers ...
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... Data bus Write TMnC Write TMmC LSCLK TMnCON0 HT BCLK TMnCON1 External clock P44/T02P0C K Read T MnC P45/T13P1C Data bus ML610Q421/ML610Q422 User’s Manual TMnCON1: Timer control register 1 TMmC, TMnC: Timer counter registers Comparator 8 TMnCON0 TnCK R TMnCON1 TMnC 8 (a) In 8-bit Timer Mode (Timers ...
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... Low-speed Timer Base Counter(LTBC) 16KHz Counter External clock P44/T02P0CK P45/T13P1CK (c ) Frequency measurement mode with 16bit timer(Timer2 to 3) Figure 10-1 Configuration of Timers ML610Q421/ML610Q422 User’s Manual 8KHz 436cycle 4KHz at 2KHz 32KHz 1KHz Decoder D Q 512Hz 256Hz 128Hz 64Hz 64Hz 437c LSCLK T M2CON0 ...
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... Timer 2 control register 0 0F03AH Timer 2 control register 1 0F03BH 0F03CH Timer 3 data register Timer 3 counter register 0F03DH Timer 3 control register 0 0F03EH Timer 3 control register 1 0F03FH ML610Q421/ML610Q422 User’s Manual Symbol (Byte) Symbol (Word) TM0D TM0DC TM0C TM0CON0 TM0CON TM0CON1 TM1D TM1DC TM1C ...
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... TM0D is a special function register (SFR) to set the value to be compared with the timer 0 counter register (TM0C) value. Note: Set TM0D when the timer stops(When T0STAT bit of TM0CON1 register is “0”). When “00H” is written in TM0D, TM0D is set to “01H”. ML610Q421/ML610Q422 User’s Manual T0D5 ...
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... TM1D is a special function register (SFR) to set the value to be compared with the value of the timer 1 counter register (TM1C). Note: Set TM1D when the timer stops(When T1STAT bit of TM1CON1 register is “0”). When “00H” is written in TM1D, TM1D is set to “01H”. ML610Q421/ML610Q422 User’s Manual T1D5 ...
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... TM2D is a special function register (SFR) to set the value to be compared with the value of the timer 2 counter register (TM2C). Note: Set TM2D when the timer stops(When T2STAT bit of TM2CON1 register is “0”). When “00H” is written in TM2D, TM2D is set to “01H”. ML610Q421/ML610Q422 User’s Manual T2D5 ...
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... TM3D is a special function register (SFR) to set the value to be compared with the value of the timer 3 counter register (TM3C). Note: Set TM3D when the timer stops(When T3STAT bit of TM3CON1 register is “0”). When “00H” is written in TM3D, TM3D is set to “01H”. ML610Q421/ML610Q422 User’s Manual T3D5 ...
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... Table 10-1 TM0C Read Enable/Disable during Timer Operation Timer clock System clock T0CK SYSCLK LSCLK LSCLK LSCLK HSCLK HTBCLK LSCLK HTBCLK HSCLK LSCLK External clock HSCLK ML610Q421/ML610Q422 User’s Manual T0C5 T 0C4 T 0C3 R/W R/W R TM0C read enable/disable Read enabled Read enabled. However, to prevent the reading of undefined data during incremental counting, read TM0C twice and check that the results match ...
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... Table 10-2 TM1C Read Enable/Disable during Timer Operation Timer clock System clock T1CK SYSCLK LSCLK LSCLK LSCLK HSCLK HTBCLK LSCLK HTBCLK HSCLK LSCLK External clock HSCLK ML610Q421/ML610Q422 User’s Manual T1C5 T 1C4 T 1C3 R/W R/W R TM1C read enable/disable Read enabled Read enabled. However, to prevent the reading of undefined data during incremental counting, read TM1C twice and check that the results match ...
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... Table 10-3 TM2C Read Enable/Disable during Timer Operation Timer clock System clock T2CK SYSCLK LSCLK LSCLK LSCLK HSCLK HTBCLK LSCLK HTBCLK HSCLK LSCLK External clock HSCLK ML610Q421/ML610Q422 User’s Manual T2C5 T 2C4 T 2C3 R/W R/W R TM2C read enable/disable Read enabled Read enabled. However, to prevent the reading of undefined data during incremental counting, read TM2C twice and check that the results match ...
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... Table 10-4 TM3C Read Enable/Disable during Timer Operation Timer clock System clock T3CK SYSCLK LSCLK LSCLK LSCLK HSCLK HTBCLK LSCLK HTBCLK HSCLK LSCLK External clock HSCLK ML610Q421/ML610Q422 User’s Manual T3C5 T 3C4 T 3C3 R/W R/W R TM3C read enable/disable Read enabled Read enabled. However, to prevent the reading of undefined data during incremental counting, read TM3C twice and check that the results match ...
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... In 16-bit timer mode, timer 0 and timer 1 are connected and they operate as a 16-bit timer. In 16-bit timer mode, timer 1 is incremented by a timer 0 overflow signal. A timer 0 interrupt (TM0INT) is not generated. T01M16 8-bit timer mode (initial value) 0 16-bit timer mode 1 ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ ⎯ T01M16 ...
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... In cases where the 16-bit timer mode has been selected by setting T01M16 of TM0CON to “1”, the values of T1CS1 and T1CS0 are invalid. T1CS1 T 1CS0 LSCLK (initial value HTBCLK 0 1 Prohibited (timer 1 does not operate External clock (P45/T13P1CK ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ ⎯ R/W R/W R Description 10 – 13 Chapter 10 Timers ...
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... Prohibited (timer 2 and timer 3 does not operate 16-bit timer frequency measurement mode • T2FMA7~T2FMA4 (bit 7~4) The T2FMA7 bit ~T2FMA4 bit shows the LSI has the frequency measurement mode. Those bits are read-only and always return 1010b on ML610Q421/ML610Q422. T 2FMA7 T 2FMA6 T 2FMA5 ML610Q421/ML610Q422 User’ ...
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... In cases where the 16-bit timer mode has been selected by setting T23M16 of TM2CON to “1”, the values of T3CS1 and T3CS0 are invalid. T3CS1 T 3CS0 LSCLK (initial value HTBCLK 0 1 Prohibited (timer 3 does not operate External clock (P45/T13P1CK ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ ⎯ R/W R/W R Description 10 – 15 Chapter 10 Timers ...
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... The T0RUN bit is used for controlling stop/start of timer 0. T0RUN Stops counting. 0 Starts counting. 1 • T0STAT (bit 7) The T0STAT bit is used for indicating “counting stopped”/”counting in progress” of timer 0. T 0STAT 0 Counting stopped. Counting in progress. 1 ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ ⎯ R/W R/W R ...
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... T1STAT (bit 7) The T1STAT bit is used for indicating “counting stopped”/”counting in progress” of timer 1. In 16-bit timer mode, this bit will read “0”. T 1STAT Counting stopped. 0 Counting in progress. 1 ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ ⎯ R/W R/W R/W ...
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... TM3INT does not occur. T2RUN Stops counting. 0 Starts counting. 1 • T2STAT (bit 7) The T2STAT bit is used for indicating “counting stopped”/”counting in progress” of timer 2. T 2STAT Counting stopped. 0 Counting in progress. 1 ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ ⎯ R/W R/W R Description Description 10 – ...
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... The T3STAT bit is used for indicating “counting stopped”/”counting in progress” of timer 3. In 16-bit timer mode and 16-bit timer frequency measurement mode, this bit will return “0”. T 3STAT Counting stopped Counting in progress. ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ ⎯ ...
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... Figure 10-2 Operation Timing Diagram of Timer Note: Even if “0” is written to the TnRUN bits, counting operation continues up to the falling edge (the timer status flag (TnSTA “1” state) of the next timer clock pulse. Therefore, the timer interrupt (TMnINT) may occur. ML610Q421/ML610Q422 User’s Manual ( ...
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... TM3CON1 register) are “0” for making certain the timer stops. (3) Set T23MFM bit (bit3 of TM2CON0 register) to “1” (Frequency measurement mode), set T23M16 bit (bit2of TM2CON0 register) to “1” (16bit mode) and set T2CS1-0 bits(bit1/0 of TM2CON0 register) to “01”(HTBCLK mode). ML610Q421/ML610Q422 User’s Manual (8) (7) 437/32768S 10 – ...
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... This indicates that 9600Hz is about 62 times the cycle of HTBCLK. Therefore, if 3DH(=3EH-1) set to the timer register and the timer start counting, the cycle of TMnINT interrupt that can occur every 62 counts of HTBCLK is: tTMnINT = (1 / 600000 0.10333ms (9677Hz) ML610Q421/ML610Q422 User’s Manual 10 – 22 Chapter 10 Timers ...
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... Round off {N1/64 (6bit right-shift (minus) 1. 9600 Round off {N1/128 (7bit right-shift (minus) 1. 19200 Round off {N1/256 (8bit right-shift (minus) 1. 38400 Round off {N1/512 (9bit right-shift (minus) 1. 57600 Round off {N1/768} - (minus) 1. ML610Q421/ML610Q422 User’s Manual 10 – 23 Chapter 10 Timers Theoretical accuracy ~ +/- 2% +/- 2% ~ 2.5% ±2.5% ~ ...
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... Round off {N1/64 (6bit right-shift (minus) 1. 9600 Round off {N1/128 (7bit right-shift (minus) 1. 19200 Round off {N1/256 (8bit right-shift (minus) 1. 38400 Round off {N1/512 (9bit right-shift (minus) 1. 57600 Round off {N1/768} - (minus) 1. ML610Q421/ML610Q422 User’s Manual 10 – 24 Chapter 10 Timers Theoretical accuracy ~ +/- 2% ±2.5% ~ ...
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Chapter 11 PWM ...
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... PWM0 duty register H PW0DBUF: PWM0 duty buffer PW0CL: PWM0 counter register L PW0CH: PWM0 counter register H PW0CON0: PWM0 control register 0 PW0CON1: PWM0 control register 1 Figure 11-1 Configuration of PWM Circuit ML610Q421/ML610Q422 User’s Manual P0NEG P0FLG Output control Period match Comparator 16 P0CK R PW0CH/L PW0PBUF ...
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... PWM0 duty register L 0F0A2H PWM0 duty register H 0F0A3H PWM0 counter register L 0F0A4H PWM0 counter register H 0F0A5H 0F0A6H PWM0 control register 0 PWM0 control register 1 0F0A7H ML610Q421/ML610Q422 User’s Manual Description Symbol (Byte) Symbol (Word) PW0PL PW0P PW0PH PW0DL PW0D PW0DH PW0CL PW0C ...
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... R/W R/W R/W At reset 1 1 PW0PH and PW0PL are special function registers (SFRs) to set the PWM0 periods. Note: When PW0PH or PW0PL is set to “0000H”, the PWM0 period buffer (PW0PBUF) is set to “0001H”. ML610Q421/ML610Q422 User’s Manual P0P5 P0P4 P0P3 R/W R/W ...
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... Access: R/W Access size: 8 bits Initial value: 00H PW0DH and PW0DL are special function registers (SFRs) to set the duties of PWM0. Note: Set PW0DH and PW0DL to values smaller than those to which PW0PH and PW0PL are set. ML610Q421/ML610Q422 User’s Manual P0D5 P0D4 ...
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... Table 11-1 PW0CH and PW0CL Read Enable/Disable during PWM0 Operation PWM clock System clock P0CK SYSCLK LSCLK LSCLK LSCLK HSCLK HTBCLK LSCLK HTBCLK HSCLK LSCLK External clock HSCLK ML610Q421/ML610Q422 User’s Manual P0C5 P0C4 P0C3 R/W R/W R P0C13 ...
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... The P0NEG bit is used to select the output logic. When the positive logic is selected, the initial value of PWM0 output is “1”, and when the negative logic is selected, the initial value of PWM0 output is “0”. P0NEG Positive logic (initial value) 0 Negative logic 1 ML610Q421/ML610Q422 User’s Manual ⎯ P0NEG P0IS1 ...
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... PWM0 output flag = “0” 0 PWM0 output flag = “1” (initial value) 1 • P0STAT (bit 7) The P0STAT bit indicates “counting stopped or “counting in progress” of PWM0. P0ST AT Counting stopped. (Initial value) 0 Counting in progress. 1 ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ ⎯ R/W R/W R/W 0 ...
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... PWP P0CK (Hz) PW0D + PWP P0CK (Hz) PWM0 period registers (PW0PH, PW0PL) setting value (0001H to 0FFFFH) PW0P: PW0D: PWM0 duty registers (PW0DH, PW0DL) setting value (0000H to 0FFFEH) Clock frequency selected by the PWM0 control register 0 (PW0CON0) P0CK: ML610Q421/ML610Q422 User’s Manual 11 – 8 Chapter 11 PWM ...
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... Even if “0” is written to the P0RUN bit, counting operation continues up to the falling edge (the PWM0 status flag (P0STAT “1” state) of the next PWM clock pulse. Therefore, the PWM0 interrupt (PW0INT) may occur. ML610Q421/ML610Q422 User’s Manual 0000 0001 0002 ...
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... Data of P43D bit (bit3 of P4D register) does not affect to the PWM output function, so don’t care the data for the function. Reg. name Bit 7 6 P47D P46D Bit name Data * * * : Bit not related to the PWM function ** : Don’t care the data. ML610Q421/ML610Q422 User’s Manual P4MOD1 register (Address: 0F225H P45MD1 P44MD1 P43MD1 P42MD1 * * 1 P4MOD0 register (Address: 0F224H) 5 ...
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... Data of P34D bit (bit4 of P3D register) does not affect to the PWM output function, so don’t care the data for the function. Reg. name Bit Bit name Data - - - : Bit does not exist Bit not related to the PWM function ** : Don’t care the data. ML610Q421/ML610Q422 User’s Manual P3MOD1 register (Address: 0F21DH P35MD1 P34MD1 P33MD1 * 1 * P3MOD0 register (Address: 0F21CH ...
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Chapter 12 Watchdog Timer ...
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Watchdog Timer 12.1 Overview This LSI incorporates a watchdog timer (WDT) that operates at a system reset unconditionally (free-run operation) in order to detect an undefined state of the MCU and return from that state. If the WDT counter ...
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Description of Registers 12.2.1 List of Registers Address Name 0F00EH Watchdog timer control register 0F00FH Watchdog timer mode register ML610Q431/ML610Q432 User’s Manual Chapter 13 Watchdog Timer Symbol (Byte) Symbol (Word) R/W ⎯ WDTCON R/W ⎯ WDTMOD R/W 12 – ...
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Watchdog Timer Control Register (WDTCON) Address: 0F00EH Access: W Access size: 8 bits Initial value: 00H 7 6 WDTCON d7 d6 R/W R/W R/W Initial value 0 0 WDTCON is a special function register (SFR) to clear the WDT ...
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Watchdog Timer Mode Register (WDTMOD) Address: 0F00FH Access: W Access size: 8 bits Initial value: 02H 7 6 ⎯ ⎯ WDTMOD R/W R/W R/W Initial value 0 0 WDTMOD is a special function register to set the overflow period ...
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Description of Operation The WDT counter starts counting after the system reset has been released and the low-speed clock oscillation start.. Write "5AH" when the internal pointer (WDP) is "0"and then the WDT counter is cleared by writing "0A5H" ...
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Figure 12-2 shows an example of watchdog timer operation. Low-speed oscillation start 2WDTMOD RESET_S System reset 3 Data: 5A WDTCON Write WDTP Internal pointer WDT counter WDTINT WDT interrupt WDT reset Figure 12-2 Example of Watchdog Timer Operation 1 The ...
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Handling example when you do not want to use the watch dog timer WDT counter is a free-run counter that starts count-up automatically after the system reset released and the low-speed clock (LSCLK) starts oscillating. If the WDT counter ...
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Synchronous Serial Port Chapter 13 ...
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... Serial port transmit/receive buffer H SIO0CON: Serial port control register SIO0MOD0: Serial port mode register 0 SIO0MOD1: Serial port mode register 1 Figure 13-1 Configuration of Synchronous Serial Port ML610Q421/ML610Q422 User’s Manual Chapter 13 Synchronous Serial Port SIO0INT P41/SCK0 P45/SCK0 Shift register P42/SOUT0 8 bits/16 bits ...
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... P41/SCK0 Synchronous clock input/output. I/O Used for the tertiary function of the P41 and P45 pins. P45/SCK0 P42/SOUT 0 Transmit data output. O Used for the tertiary function of the P42 and P46 pins. P46/SOUT 0 ML610Q421/ML610Q422 User’s Manual Chapter 13 Synchronous Serial Port Description 13 – 2 ...
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... L Serial port 0 transmit/receive 0F281H buffer H Serial port 0 control register 0F282H Serial port 0 mode register 0 0F284H Serial port 0 mode register 1 0F285H ML610Q421/ML610Q422 User’s Manual Chapter 13 Synchronous Serial Port Symbol (Byte) Symbol (Word) SIO0BUFL SIO0BUF SIO0BUFH ⎯ SIO0CON SIO0MOD0 SIO0MOD SIO0MOD1 13 – ...
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... When data is written in SIO0BUFL and SIO0BUFH, the data is written in the transmit registers (SIO0TRL and SIO0TRH) and when data is read from SIO0BUFL and SIO0BUFH, the contents of the receive registers (SIO0RCL and SIO0RCH) are read. ML610Q421/ML610Q422 User’s Manual S0B5 ...
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... The S0EN bit is used to specify start of synchronous serial communication. Writing a “1” to this bit starts 8-/16-bit data communication. This bit is set to “0” automatically when 8-/16-bit data communication is terminated. The S0EN bit is set to “0” system reset. S0EN Stops communication. (Initial value) 0 Starts communication 1 ML610Q421/ML610Q422 User’s Manual Chapter 13 Synchronous Serial Port ⎯ ⎯ ⎯ ...
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... Note: • Do not change any of the SIO0MOD0 register settings during transmission/reception. • When the synchronous serial port is used, the tertiary functions of GPIO must be set. For the tertiary functions of Port 4, see Chapter 21, “Port 4”. ML610Q421/ML610Q422 User’s Manual Chapter 13 Synchronous Serial Port ⎯ ...
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... The S0CKT bit is used to select a tansfer clock output phase. S0CKT Clock type 0: Clock is output with a “H” level being the default. (Initial value) 0 Clock type 1: Clock is output with a “L” level being the default. 1 ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ S0CKT ...
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... Figure 13-2 Transmit Operation Waveforms of Synchronous Serial Port for Clock Type 0 (8-bit Length, LSB first) S0EN SCK0 SIO0T RL SOUT0 SIO0INT Figure 13-3 Transmit Operation Waveforms of Synchronous Serial Port for Clock Type 1 (8-bit Length, LSB first) ML610Q421/ML610Q422 User’s Manual Chapter 13 Synchronous Serial Port Transmit data Transmit data ...
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... Figure 13-5 Receive Operation Waveforms of Synchronous Serial Port for Clock Type 1 (8-bit Length, MSB first) Note: When the SOUT0 pin is set to the tertiary function output in receive mode, a “H” level is output from the SOUT0 output pin. ML610Q421/ML610Q422 User’s Manual Chapter 13 Synchronous Serial Port ...
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... Figure 13-6 shows the transmit/receive operation waveforms of the synchronous serial port (16-bit length, LSB first, clock types 0). S0EN SCK0 SIO0TRH,L SOUT0 SIN0 Shift register SIO0RCH, L SIO0INT Figure 13-6 Transmit/Receive Operation Waveforms of Synchronous Serial Port (16-bit Length, LSB first, Clock Type 0) ML610Q421/ML610Q422 User’s Manual Transmit data ...
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... Reg. name Bit 7 6 P47D P46D Bit name Data * * * : Bit not related to the SSIO function ** : Don’t care the data $ : Arbitrarily ML610Q421/ML610Q422 User’s Manual Chapter 13 Synchronous Serial Port P4MOD1 register (Address: 0F225H P45MD1 P44MD1 P43MD1 * * * P4MOD0 register (Address: 0F224H) 5 ...
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... Bit 7 6 P47D P46D Bit name Data * * * : Bit not related to the SSIO(using P42, P41, and P40) function ** : Don’t care the data $ : Arbitrarily ML610Q421/ML610Q422 User’s Manual Chapter 13 Synchronous Serial Port P4MOD1 register (Address: 0F225H P45MD1 P44MD1 P43MD1 * * * P4MOD0 register (Address: 0F224H) ...
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... Reg. name Bit 7 6 P47D P46D Bit name Data * ** - : Bit not related to the SSIO(using P46, P45, and P44) function ** : Don’t care the data $ : Arbitrarily ML610Q421/ML610Q422 User’s Manual Chapter 13 Synchronous Serial Port P4MOD1 register (Address: 0F225H P45MD1 P44MD1 P43MD1 P42MD1 ...
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... Reg. name Bit 7 6 P47D P46D Bit name Data * ** - : Bit not related to the SSIO(using P46, P45, and P44) function ** : Don’t care the data $ : Arbitrarily ML610Q421/ML610Q422 User’s Manual Chapter 13 Synchronous Serial Port P4MOD1 register (Address: 0F225H P45MD1 P44MD1 P43MD1 P42MD1 ...
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... ML610Q421/ML610Q422 User’s Manual 14 – 1 Chapter 14 UART Chapter 14 UART ...
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... UA0MOD0, 1: UA0STAT: 14.1.3 List of Pins Pin name I/O P02/RXD0 I P42/RXD0 I P43/TXD0 O ML610Q421/ML610Q422 User’s Manual Shift Register UART Controller UA0CON UA0BUF UA0MOD0, 1 UART0 transmit/receive buffer UART0 baud rate registers H, L UART0 control register UART0 mode registers 0, 1 UART0 status register Figure 14-1 Configuration of UART ...
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... UART0 control register 0F292H UART0 mode register 0 0F293H UART0 mode register 1 0F294H UART0 baud rate register L 0F295H UART0 baud rate register H 0F296H UART0 status register ML610Q421/ML610Q422 User’s Manual Symbol (Byte) Symbol (Word) R/W ⎯ UA0BUF R/W ⎯ UA0CON R/W UA0MOD0 R/W ...
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... The bits not required when 5-bit, 6-bit, 7-bit, or 8-bit data length is slected become invalid in transmit mode and are set to “0” in receive mode. Note: For operation in transmit mode, be sure to set the transmit mode (UA0MOD0 and UA0MOD1) before setting transmit data in UAOBUF. ML610Q421/ML610Q422 User’s Manual U0B5 ...
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... The U0EN bit is used to specify the UART communication operation start. When U0EN is set to “1”, UART communication starts. In transmit mode, this bit is automatically set to “0” at termination of transmission. In receive mode, receive operation is continued. To terminate reception, set the bit to “0” by software. U0EN 0 Stops communication. (Initial value) 1 Starts communication. ML610Q421/ML610Q422 User’s Manual ⎯ ⎯ ⎯ R/W ...
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... When selecting the P42 pin as the receive data input pin necessary to configure settings for the Port 4 secondary functions. For the details of the Port 4 secondary function settings, see Chapter 21, “Port 4”. ML610Q421/ML610Q422 User’s Manual — ...
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... The U0STP bit is used to select the stop bit length in the communication of the UART. U0S stop bit (initial value stop bits • U0NEG (bit 5) The U0NEG bit is used to select positive logic or negative logic in the communication of the UART. U0NEG 0 Positive logic (initial value) 1 Negative logic ML610Q421/ML610Q422 User’s Manual U0NEG U0S TP U0PT1 R/W R/W R ...
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... The U0DIR bit is used to select LSB first or MSB first in the communication of the UART. U0DIR 0 LSB first (initial value) 1 MSB first Note: Always set the UA0MOD1 register while communication is stopped, and do not rewrite it during communication. ML610Q421/ML610Q422 User’s Manual Description 14 – 8 Chapter 14 UART ...
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... For the relationship between the count value of the baud rate generator and baud rate, see Section 14.3.2, “Baud Rate”. Note: Always set the UA0BRTL and UA0BRTH registers while communication is stopped, and do not rewrite them during communication. ML610Q421/ML610Q422 User’s Manual ...
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... When the parity of the received data and the parity bit attached to the data do not coincide, this bit is set to “1”. U0PER is updated whenever data is received. The U0PER bit is fixed to “0” in transmit mode. U0PER 0 No parity error (initial value) 1 Parity error ML610Q421/ML610Q422 User’s Manual — — U0FUL U0PE R ...
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... UA0BUF after checking that the U0FUL flag has been set to “0”. The U0FUL bit is fixed to “0” in receive mode. U0F UL 0 There is no data in the transmit/receive buffer. (Initial value) 1 There is data in the transmit/receive buffer. ML610Q421/ML610Q422 User’s Manual Description 14 – 11 Chapter 14 UART ...
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... Figure 14-2 Positive Logic Input/Output Format Start 1 2 bit • 1 frame Max. ……… 12 bits Min. ……… 7 bits Figure 14-3 Negative Logic Input/Output Format ML610Q421/ML610Q422 User’s Manual 1 frame Data bit • Data bit length……….. bits variable • ...
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... When specifying 65.536 kHz (LSCLK×2) for the clock, enable the operation of the 2×low-speed clock by setting bit 2 (ENMLT) of the frequency control register 1 (FCON1) to “1”. Compensating tolerant of RC oscillation 500kHz with Timer can support errors of +/- 2% or less at 9600bps. See Section 10.3.2., “Frequency measurement mode”. ML610Q421/ML610Q422 User’s Manual Clock frequency (Hz) –1 Baud rate (bps) ...