ML610Q422-NNNTBZ03A7 Rohm Semiconductor, ML610Q422-NNNTBZ03A7 Datasheet - Page 204

• Manufacturer Part Number: ML610Q422-NNNTBZ03A7
• Description: MCU 8BIT 32K FLASH 22CH 120-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q422-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.3.5
Reception is started by selecting a receive data input pin using the U0RSEL bit of the UART0 mode register 0
(UA0MOD0), then setting the U0IO bit of UA0MOD0 to “0” to select receive mode, and then setting the U0EN bit of
the UART0 control register (UA0CON) to “1”.
Figure 14-6 shows the operation timing for reception.
When receive operation starts, the LSI checks the data sent to the input pin RXD0 and waits for the arrival of a start bit.
When detecting a start bit (2), the LSI generates the internal transfer clock of the baud rate set with the start bit detect
point as a reference and performs receive operation.
The shift register shifts in the data input to RXD on the rising edge of the internal transfer clock. The data and parity
bit are shifted into the shift register and 5- to 8- bit receive data is transferred to the transmit/receive buffer (UA0BUF)
concurrently with the fall of the internal transfer clock of 3.
The LSI requests a UART0 interrupt on the rising edge of the internal transfer clock subsequent to the internal transfer
clock by which the receive data was fetched (4) and checks for a stop bit error and a parity bit error. When an error is
detected, the LSI sets the corresponding bit of the UART0 status register (UA0STAT) to “1”.
Parity error
Overrun error
Framing error
As shown in Figure 14-6, the rise of the internal transfer c lock is set so that it may fall into the middle of the bit interval
of the receive data.
Reception continues until the U0EN bit is reset to “0” by the program. When the U0EN bit is reset to “0” during
reception, the data received may be destroyed. When the U0EN bit is reset to “0” during the “U0EN reset enable
period” in Figure 14.6, the data received is protected.
Receive Operation
: S0PER = “1”
: S0OER = “1”
: S0FER = “1”
14 – 17
ML610Q421/ML610Q422 User’s Manual
Chapter 14 UART