AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 82

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
82
2
1
0
Single Slot Support [SSS_L]. Read Only. This CSR being asserted (low) indicates there is a single
slot present. If it is inactive, there may be multiple slots present. This CSR is latched from
[B,A]_GNT_L4 at the rising edge of PWROK and the information is used for several purposes:
Conventional PCI Mode Frequency [CPCI66]. Read Only. If Dev[B,A]:0x60[SCF] = 0h, then the
bridge is in conventional PCI mode and this bit is valid. Otherwise, its state is undefined.
0 = [B,A]_PCLK[4:0] toggle at 33 MHz.
1 = [B,A]_PCLK[4:0] toggle at 66 MHz.
Note: The default state for this field is determined by strapping options described in section 2.5.
Non-IOAPIC Mode [NIOAMODE]. Read-Write. This bit is used to enable [B,A]_PIRQ[D,C,B,A]_L to
the NIOAIRQ[D,C,B,A]_L pins.
0 = The state of the PIRQ[D:A]_L pins are not OR’d into the NIOAIRQ[D:A]_L pins. See the equation
1 = The state of the PIRQ[D:A]_L pin from the bridge is OR’d with the state from the other bridge and
Similarly for NIOAIRQ[C and D]_L, where RDR[B,A][3:0][IM] is the interrupt mask field of the
redirection register (see section 3.6), [B,A] = the bridge letter; [3:0] = the redirection register index.
Note: The NIOAIRQ[D:A]_L pins are open drain outputs. So a high on the PIRQ input is translated to the high
• Hot-Plug:
• PCIXCAP:
• PCI-X Mode 2:
NIOAIRQA_L = ~( DevA:0x40[NIOAMODE] & ~A_PIRQA_L & RDRA0[IM]
NIOAIRQB_L = ~( DevA:0x40[NIOAMODE] & ~A_PIRQB_L & RDRA1[IM]
below.
passed to the NIOAIRQ[D:A]_L pin. This is shown in the following equations:
If SSS_L is low, then there is only one slot. This slot is required to use [B,A]_REQ_L0,
[B,A]_GNT_L0, and [B,A]_PCLK0, rather than any of the other REQ/GNT/CLK signals. In this
mode, [B,A]_GNT_L1 is redefined to be an IDSEL line for an external device; [B,A]_REQ_L1 is
redefined to be a VIOSEL signal for the power supply; and [B,A]_PCLK1 is redefined to be a
VIOEN signal for the power supply.
If SSS_L is high, [B,A]_GNT_L1 and [B,A]_REQ_L1 are available for use as request lines for PCI
slots and [B,A]_PCLK1 is available for use as a PCI clock.
If the bridge is in hot-plug mode as specified by Dev[B,A]:0x48[HPEN] and SSS_L is low, then
the bridge supports a single hot-plug slot without external isolation switches. In this mode,
external isolation switches between the AMD-8132 tunnel and the slot are not required and
should not be used. See section 1.3.7.
If the bridge is in hot-plug mode as specified by Dev[B,A]:0x48[HPEN] and SSS_L is high, then
the bridge requires external isolation switches for all hot-plug slots.
If SSS_L is low, this indicates there is a single slot present and it may be a PCI-X
capable slot. The bridge will compare the PCIXCAP input to the five voltage levels used by PCI-X
Mode 2 devices.
If SSS_L is high, this indicates there may be multiple slots present. If there are multiple slots
present, then they cannot be Mode 2 capable (the MODE2 connector pin must not be asserted to
these slots). The bridge will compare the PCIXCAP input to the three voltage levels used by
PCI-X Mode 1 devices.
impedance state on the NIOAIRQ output. See section 1.3.2 for more details about interrupt routing. It is
expected that this bit is normally left high by system BIOS.
| DevB:0x40[NIOAMODE] & ~B_PIRQA_L & RDRB0[IM] );
| DevB:0x40[NIOAMODE] & ~B_PIRQB_L & RDRB1[IM] );
®
2.0 Tunnel Data Sheet
Registers
26792 Rev. 3.07 July 2005
®
Mode 2
Chapter 3