AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 124

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
Dev[B,A]:1xD4
Default: See individual fields.
This block of CSRs provides a mechanism where by the HyperTransport calibration block can be controlled
solely by reading and writing CSRs and is active when the CSR HT_DIRECT is asserted.
Dev[B,A]:1xD8
Default: See individual fields.
124
Bits
31
30
29
28
27:22
21
20
19:16
15
14:10
9
8
6:0
Bits
31:30
29
7
Description
HT_DIRECT.
Default = value of CMPOVR pin at rising edge of PWROK
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
I_REF. When HT_DIRECT is asserted, this CSR directly controls the I_REF port of the
HyperTransport™ calibration block.
Default = 0x0
RX_REF_UPDATE. When HT_DIRECT is asserted, this CSR directly controls the RX_REF_UPDATE
port of the HyperTransport™ calibration block.
Default = 0b
Reserved.
Reserved.
Reserved.
TX_PHY_UPDATE. When HT_DIRECT is asserted, this CSR directly controls the TX_PHY_UPDATE
port of the HyperTransport™ calibration block.
Default = 0b
Reserved.
Description
Reserved.
IREFUPDATE. This csr should be set to 1 when a new set of IREF CSR values is present. This CSR
is written to 0 by the hardware when it has absorbed the new values. The associated CSRs are
Dev[B,A]:1xC8[IREFCOMPREF, IREFINVDIFFSE, IREFADJ]; Dev[B,A]:1xD0[IREFBYPINVDIFFSE];
Dev[B,A]:1xE0[IREF_MIN, IREF_MAX].
Default = 1b
• When asserted, the pins of the HyperTransport™ calibration block are controlled directly by the
• When clear, the HyperTransport calibration block is controlled by a block of hardware that
CSRs in the doubleword 1xD4.
automatically derives the HyperTransport calibration values before applying them to the pads.
®
2.0 Tunnel Data Sheet
Registers
26792 Rev. 3.07 July 2005
Attribute: Read-Write
Attribute: Read-Write
Chapter 3