AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 140

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
SHPC SERR Locator
Default: 0000 0000h
SHPC SERR-INT
The SHPC interrupt shown below either generates an interrupt packet based on the SHPC_INTR IOAPIC
entry, or asserts the signal [B,A]_PIRQA_L if the SHPC_INTR RDR[IM] is set and
Dev[B,A]:0x04[INTDISABLE] is not set.
SHPC_WAKEUP = (SHPC[B,A]:18[IP] != 0000b)
The SHPC interrupt shown below is routed to the [B,A]_PIRQA_L pin.
SHPC_INTR = ~SHPC[B,A]:20[GIM] & SHPC_WAKEUP;
The SHPC system error shown below sets Dev[B,A]:0x1C[RSE] (also see Dev[B,A]:0x3C[SERREN]).
SHPC_SERR = ~SHPC[B,A]:20[GSERRM] &
Default: 0000 000Fh
140
Bits
31:5
4:1
0
Bits
31:18
17
16
15:4
3
2
Description
Reserved.
Slot SERR Pending [SERRP[4:1]]. Each bit n of this field corresponds to slot n.
1 = A slot status bit capable of generating SERR is set and the corresponding SERR mask is 0. Slot
Arbiter SERR Pending [A_SERRP].
1 = SHPC[B,A]:20[ATOUT_STS] is 1 and SHPC[B,A]:20[A_SERRM] is 0.
Description
Reserved.
Arbiter Timeout Status [ATOUT_STS]. Read. Set by hardware. Write 1 to clear. Set when an arbiter
timeout is detected by the SHPC logic. The arbiter timeout occurs when the PCI bus is requested
(from the internal arbiter) for a hot-plug operation and it is not granted for 2
Command Completion Status [CC_STS]. Read. Set by hardware. Write 1 to clear. Set when an
SHPC[B,A]:16[BSY] transition from 1 to 0 is detected.
Reserved.
Arbiter SERR Mask [A_SERRM]. Read-Write.
1 = SERR indication for arbiter timeout is disabled.
Command Complete Interrupt Mask [CC_IM]. Read-Write.
1 = SHPC interrupt generation for command completion is disabled.
status bits capable of generating SERR are SHPC[B,A]:[30, 2C, 28, 24][MRLSC_STS, CPF_STS].
The corresponding SERR masks are SHPC[B,A]:[30, 2C, 28, 24][MRLS_SERRM, CPF_SERRM].
( (SHPC[B,A]:1C[SERRP] != 0000b)
| ~SHPC[B,A]:20[A_SERRM] & SHPC[B,A]:20[ATOUT_STS]);
| ~SHPC[B,A]:20[CC_IM] & SHPC[B,A]:20[CC_STS];
®
2.0 Tunnel Data Sheet
Registers
23
26792 Rev. 3.07 July 2005
[B,A]_PCLK cycles.
Attribute: Read Only
Attribute: See Below
SHPC[B,A]:1C
SHPC[B,A]:20
Chapter 3