AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 27

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
Prefetch CSR values should not be changed while reads from the PCI bus to HyperTransport are outstanding or
the resulting behavior is undefined. The PCI bus should be quiesced and any active buffers allowed time to
discard before CSR values are changed.
1.3.5
The bridges claim no upstream HyperTransport requests, but do claim the following downstream
HyperTransport requests if the COMPAT bit is clear:
Chapter 1
• In no event does prefetching continue past an address range boundary to an address for which the
• A requested prefetch is allowed to burst until it is complete or until the master terminates the burst.
• If the master terminates a burst, all requested and unrequested prefetch data is discarded if
• If the AMD-8132 tunnel terminates a burst because the required next data line was not acquired and if
• If the discard timer times out for the initial data transfer, then all requested and unrequested prefetch data is
• If a burst is terminated for any reason and the data is not discarded, a separate discard timer value
• The Dev[B,A]:0x4C[MRD_ALIAS] bit can be asserted to relax the requirements for reconnection. For
• Prefetching automatically stops when a memory window boundary defined by the configuration registers
• If Dev[B,A]:0x4C[DPDH] is asserted, all unrequested prefetch data is discarded when a host request is
• If Dev[B,A]:0x4C[DPDMAC] is asserted, all unrequested prefetch data for a particular master is discarded
• The AMD-8132 tunnel can prefetch for up to eight PCI requests at a time, limited by
• All requests to memory and I/O space specified by Dev[B,A]:0x[30:1C] if
• All configuration and extended configuration requests to the implemented functions of DevA or DevB
• All configuration and extended configuration requests to buses behind bridge A or bridge B.
AMD-8132 tunnel would not be a PCI bus target. Range boundaries that are checked include:
Dev[B,A]:0x4C[DPDMD_L] is asserted for that master.
Dev[B,A]:0x4C[DPDTD] is asserted, all unrequested prefetch data for that request is discarded as it
arrives. Note that DPDTD should only be set if all Dev[B,A]:0x4C[20:16] DPDMD_L bits are 0 for that
bridge. Setting DPDTD when any DPDMD_L bits are set may result in undefined behavior.
discarded and Dev[B,A]:0x3C[DTS] is set and an error may be signalled.
controlled by Dev[B,A]:0x4C[URP_TIMER] is used for reconnections. This timer measures the time
between the point of disconnection to when the master attempts to reconnect, regardless of whether the
AMD-8132 tunnel has acquired the data. The timer restarts every time reconnection is attempted, whether
or not data is transferred. If the timer expires, all prefetched data is discarded but no error is logged.
example, if the bit is set and a master issues an MRM for a long burst but then switches to MRL to
complete the burst after being disconnected near the end, the MRL will be allowed to reconnect and
receive the unrequested prefetch data fetched by the MRM.
is reached. Optionally, based on Dev[B,A]:0x4C[PFDISC_4K] the prefetch stops on 4-K boundaries.
issued by the AMD-8132 tunnel onto the PCI bus.
if that master issues a read request that does not hit the acquired lines.
Dev[B,A]:0x4C[OUTSTDELREQ]. Additionally, Dev[B,A]:0x4C[SDRPM] can be set to prevent a single
master from having more than one outstanding request. If a request is received that would violate either of
these limits, it is retried.
Dev[B,A]:0x04[MEMEN, IOEN] are set.
(also see section 3.1.1).
• top of 64-bit memory address space
• top of 40-bit memory address space (FD_0000_0000h)
• non-prefetchable memory base, if enabled (Dev[B,A]:0x[D8,20])
• prefetchable memory base, if enabled (Dev[B,A]:0x[28,24])
• base of VGA memory space, if enabled (A_0000h)
HyperTransport™ Requests Claimed by the Bridges
Functional Operation
AMD-8132™ HyperTransport™ PCI-X
®
2.0 Tunnel Data Sheet
27