AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 25

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
1.3.2.4
There is an alternative method of delivering interrupt information over HyperTransport. Transitions on the PCI
interrupt pins can cause INTx virtual wire packets to be issued on the upstream HyperTransport link instead of
HyperTransport interrupt packets. Generation of INTx virtual wire packets is enabled with
Dev[B,A]:0x48 [INTx_PACKET_EN].
1.3.3
Write chaining refers to issuing two or more write requests from the HyperTransport bus as a single PCI or
PCI-X operation. Write chaining is used to maximize available PCI or PCI-X bandwidth by avoiding the
protocol overhead of issuing multiple operations that would each have its own address/attribute phases, wait
states, and turnaround cycles.
The AMD-8132 tunnel implements chaining posted WrSized requests from the HyperTransport bus under the
following conditions:
If these conditions are all true when the AMD-8132 tunnel posted channel for one of its bridges wins internal
arbitration over the nonposted and response channels to issue its traffic to the PCI or PCI-X bus, up to four
WrSized requests from the HyperTransport bus are issued as as a single PCI Memory Write or Memory Write
and Invalidate or PCI-X Memory Write Block operation.
1.3.4
Prefetching refers to the acquisition of memory read data from the host prior to the master’s request for the
data. When using the internal arbiter, prefetching in conventional PCI mode is enabled on a per-master basis
through Dev[B,A]:0x40[PFEN[4:0]_L]. When using an external arbiter, the prefetching logic cannot
distinguish between masters and all traffic is treated as if coming from master 0.
The following are definitions used in the rules for prefetching:
Chapter 1
• The writes must be posted Doubleword WrSized requests (as opposed to byte-sized requests) that are all
• The address of the last doubleword of one write must be adjacent to the address of the first doubleword of
• For the targeted AMD-8132 tunnel bridge, the WriteChainEnable bit Dev[B,A]:0x40[31] must be set.
• The data for all writes must have been received by the AMD-8132 tunnel internal buffers. A write whose
• The writes must not have the COMPAT bit set in the HyperTransport request.
• The writes must not have data errors, or the Downstream Post Data Error Disable bit DevA:0xDC[6] must
• The PassPW, UnitID, SeqID, Isoc, and Coherent attributes in the HyperTransport request packets must be
• Memory Read: any of the three PCI commands for reading memory - MR (Memory Read), MRL (Memory
targeted to the same secondary PCI or PCI-X bus below the AMD-8132 tunnel. Doubleword WrSized
requests from one to sixteen doublewords in size can be chained.
the subsequent write. The addresses spanned by the writes must not cross a 128-byte (32-doubleword)
address boundary; e.g., a PCI-X ADB, although this restriction also applies to conventional PCI secondary
buses.
data is still being transferred across the HyperTransport bus won't be chained.
be set.
the same for all writes in the chain.
Read Line), or MRM (Memory Read Multiple). In this section, memory read is a collective term for all
three types of reads. When a specific type of memory read is meant, its acronym is used.
INTx Virtual Wire Messages
Write Chaining
Prefetching In Conventional PCI Mode
Functional Operation
AMD-8132™ HyperTransport™ PCI-X
®
2.0 Tunnel Data Sheet
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