ALXD800EEXJ2VD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD C3 Datasheet - Page 507

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ALXD800EEXJ2VD C3

Manufacturer Part Number
ALXD800EEXJ2VD C3
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of ALXD800EEXJ2VD C3

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
Video Input Port Register Descriptions
6.10.2.27 VIP FIFO Address (VIP_FIFO_R_W_ADDR)
VIP Memory Offset 70h
Type
Reset Value
6.10.2.28 VIP FIFO Data (VIP_FIFO_DATA)
VIP Memory Offset 74h
Type
Reset Value
AMD Geode™ LX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:9
31:0
Bit
8:0
Bit
Name
RSVD
FIFO_ADDRESS
Name
FIFO_DATA
R/W
00000000h
R/W
xxxxxxxxh
Description
FIFO Data. When the FF_R/W bit is set (VIP Memory Offset 04h[24] = 1), data written to
this register is stored in FIFO_ADDR (VIP Memory Offset 70h[7:0]). When the FF_R/W
bit is reset, data from the FIFO corresponding to the address in the FIFO_ADDR is
returned
Description
Reserved. Set to 0.
FIFO ADDRESS. FIFO address for which a FIFO read or write occurs. The data is writ-
ten/read via the FIFO Data register (VIP Memory Offset 74h). Note that the 256x64 bit
FIFO is mapped as a 512x32 bit memory.
VIP_FIFO_R_W_ADDR Bit Descriptions
VIP_FIFO_R_W_ADDR Register Map
RSVD
VIP_FIFO_DATA Bit Descriptions
VIP_FIFO_DATA Register Map
FIFO_DATA
9
9
8
8
33234H
7
7
6
6
FIFO_ADDRESS
5
5
4
4
3
3
2
2
1
1
507
0
0

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