ALXD800EEXJ2VD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD C3 Datasheet - Page 221

• Manufacturer Part Number: ALXD800EEXJ2VD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ Memory Controller Register Descriptions
6.2.1.4
MSR Address
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:32
31:17
15:1
Bit
16
0
GLD Error MSR (GLD_MSR_ERROR)
Name
RSVD
RSVD
ERR_VAL0
RSVD
ERR_MASK0
ERRVAL[15:1] (RSVD)
20002003h
R/W
00000000_00000000h
Description
Reserved.
Reserved.
Error Value 0. Synchronous error flag, sent out with GLIU response packet. Hardware
sets error value; writes of 1 clears the error. The GLMC only implements the ‘type-excep-
tion’ error on bit 16, which is set when the GLIU request’s type field is either an I/O type
or snoop type. This bit will be set on such error condition, regardless of the value of
ERR_MASK0. An asynchronous error is also flagged via the mb_p_err output signal.
Note that when an error condition exists, the response packet that corresponds with the
GLIU request that caused the error may be returned to the GLIU out of order (i.e., ahead
of response data for older, outstanding requests in the GLMC). Moreover, the older, out-
standing requests may return corrupt data. (Default = 0)
Reserved.
Error Mask 0. Masks the corresponding error in bit 16. The GLMC only implements error
mask 0 that corresponds to error bit 16. This bit masks the reporting of the error event
recorded in bit 16. (Default = 0h)
GLD_MSR_ERROR Bit Descriptions
GLD_MSR_ERROR Register Map
RSVD
ERRMAS[15:1] (RSVD)
9
8
33234H
7
6
5
4
3
2
1
221
0