ALXD800EEXJ2VD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD C3 Datasheet - Page 506

• Manufacturer Part Number: ALXD800EEXJ2VD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.10.2.25 VIP Page Offset/ Page Count (VIP_PAGE_OFFSET
VIP Memory Offset 68h
Type
Reset Value
6.10.2.26 VIP Vertical Start/Stop (VIP_VERT_START_STOP
VIP Memory Offset 6Ch
Type
Reset Value
506
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
31:28
27:16
15:12
31:0
11:0
Bit
Bit
RSVD
Name
PAGE_OFFSET
Name
RSVD
VERT_END
RSVD
VERT_START
R/W
00000000h
R/W
00000000h
33234H
Description
Page Offset. This register specifies the offset to the next page of buffer data. If the page
count is 2 or greater, the next frame of data is started at an address of buffer +
PAGE_OFFSET. Up to eight pages (frames) can be accumulated. The address of the
next frame is located at a “Page Offset” address. Note that ancillary data and MSG/
STRM data is not paged. This only applies to video and VBI data. The value in this regis-
ter needs to be 32-byte aligned. (Bits [4:0] are required to be 00000.)
VERT_END
Description
Reserved. Set to 0.
Vertical End Capture. This register specifies the last line # in a field/frame that is cap-
tured when the subwindow capture function is enabled in non BT.601 modes. In BT.601
interlaced modes, this register determines when the odd field line capture completes. In
601 non-interlaced modes, this register determines when the video capture completes.
See Figure 6-48 "BT.601 Mode Vertical Timing" on page 473 for additional detail.
Reserved. Set to 0.
Vertical Start Capture. This register specifies the first line # in a field/frame that is cap-
tured when the subwindow capture function is enabled in non 601 modes. In BT.601
interlaced modes, this register determines when the odd field video capture starts. In
BT.601 non-interlaced modes, this register determines when the video capture starts.
See Figure 6-48 "BT.601 Mode Vertical Timing" on page 473 for additional detail.
VIP_VERT_START_STOP Register Map
VIP_VERT_START_STOP Bit Description
VIP_PAGE_OFFSET Bit Descriptions
VIP_PAGE_OFFSET Register Map
PAGE_OFFSET
)
)
RSVD
AMD Geode™ LX Processors Data Book
Video Input Port Register Descriptions
9
8
8
VERT_START
7
7
6
6
5
5
4
4
Program to 00000
3
3
2
2
1
1
0
0