ALXD800EEXJ2VD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD C3 Datasheet - Page 428
ALXD800EEXJ2VD C3
Manufacturer Part Number
ALXD800EEXJ2VD C3
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.ALXD800EEXJ2VD_C3.pdf
(680 pages)
Specifications of ALXD800EEXJ2VD C3
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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6.8.3.8
VP Memory Offset 038h
Type
Reset Value
6.8.3.9
VP Memory Offset 040h
Type
Reset Value
428
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:24
63:8
23:0
Bit
7:0
Bit
Palette Data (PDR)
Palette Address (PAR)
Name
RSVD (RO)
PAL_ADDR
Name
RSVD (RO)
PAL_DATA
RSVD
R/W
00000000_000000xxh
R/W
00000000_00xxxxxxh
33234H
Description
Reserved (Read Only). Reads back as 0.
Gamma Address. Specifies the address to be used for the next access to the Palette
Data register (VP Memory Offset 040h[23:0]). Each access to the PDR automatically
increments the PAR. If non-sequential access is made to the palette, the PAR must be
loaded between each non-sequential data block.
Description
Reserved (Read Only). Reads back as 0.
Palette Data. Contains the read or write data for a Gamma Correction RAM (palette).
Provides the video palette data. The data can be read or written to the Gamma Correc-
tion RAM (palette) via this register. Prior to accessing this register, an appropriate
address should be loaded to the PAR (VP Memory Offset 038h[7:0]). Subsequent
accesses to the PDR cause the internal address counter to be incremented for the next
cycle.
Note:
When a read or write to the Gamma Correction RAM occurs, the previous output
value is held for one additional DOTCLK period. This effect should go unnoticed
during normal operation.
RSVD
PDR Bit Descriptions
PAR Bit Descriptions
PDR Register Map
PAR Register Map
RSVD
RSVD
PAL_DATA
AMD Geode™ LX Processors Data Book
Video Processor Register Descriptions
9
9
8
8
7
7
6
6
5
5
PAL_ADDR
4
4
3
3
2
2
1
1
0
0
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