FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 8

• Manufacturer Part Number: FW82801EB S L73Z
• Manufacturer: Intel

Specifications of FW82801EB S L73Z

• Lead Free Status / RoHS Status: Not Compliant

Contents
8
5.9
5.10
5.11
5.12
5.13
5.8.5
5.8.6
Advanced Interrupt Controller (APIC) (D31:F0)................................................................ 130
5.9.1
5.9.2
5.9.3
5.9.4
Serial Interrupt (D31:F0) ................................................................................................... 135
5.10.1 Start Frame.......................................................................................................... 135
5.10.2 Data Frames ........................................................................................................ 136
5.10.3 Stop Frame .......................................................................................................... 136
5.10.4 Specific Interrupts Not Supported via SERIRQ ................................................... 136
5.10.5 Data Frame Format ............................................................................................. 137
Real Time Clock (D31:F0) ................................................................................................ 137
5.11.1 Update Cycles ..................................................................................................... 138
5.11.2 Interrupts.............................................................................................................. 138
5.11.3 Lockable RAM Ranges ........................................................................................ 139
5.11.4 Century Rollover .................................................................................................. 139
5.11.5 Clearing Battery-Backed RTC RAM .................................................................... 139
Processor Interface (D31:F0) ........................................................................................... 141
5.12.1 Processor Interface Signals................................................................................. 141
5.12.2 Dual-Processor Issues......................................................................................... 143
5.12.3 Speed Strapping for Processor............................................................................ 144
Power Management (D31:F0) .......................................................................................... 146
5.13.1 Features............................................................................................................... 146
5.13.2 Intel
5.13.3 System Power Planes.......................................................................................... 148
5.13.4 Intel
5.13.5 SMI#/SCI Generation........................................................................................... 148
5.8.4.6
5.8.4.7
5.8.4.8
5.8.4.9
5.8.4.10 Automatic End of Interrupt Mode ......................................................... 128
Masking Interrupts ............................................................................................... 129
5.8.5.1
5.8.5.2
Steering PCI Interrupts ........................................................................................ 129
Interrupt Handling ................................................................................................ 130
Interrupt Mapping................................................................................................. 130
PCI Message-Based Interrupts............................................................................ 131
5.9.3.1
Front Side Bus Interrupt Delivery......................................................................... 133
5.9.4.1
5.9.4.2
5.9.4.3
5.9.4.4
5.12.1.1 A20M# (Mask A20) .............................................................................. 141
5.12.1.2 INIT# (Initialization) .............................................................................. 141
5.12.1.3 FERR#/IGNNE# (Numeric Coprocessor Error /
5.12.1.4 NMI (Non-Maskable Interrupt) ............................................................. 143
5.12.1.5 Stop Clock Request and CPU Sleep
5.12.1.6 CPU Power Good (CPUPWRGOOD) .................................................. 143
5.12.2.1 Signal Differences................................................................................ 143
5.12.2.2 Power Management............................................................................. 144
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ICH5 and System Power States ................................................................ 146
ICH5 Power Planes ................................................................................... 148
Cascade Mode..................................................................................... 128
Edge and Level Triggered Mode.......................................................... 128
End of Interrupt Operations.................................................................. 128
Normal End of Interrupt........................................................................ 128
Masking on an Individual Interrupt Request......................................... 129
Special Mask Mode.............................................................................. 129
Registers and Bits Associated with PCI Interrupt Delivery .................. 132
Edge-Triggered Operation ................................................................... 133
Level-Triggered Operation ................................................................... 133
Registers Associated with Front Side Bus Interrupt Delivery............... 133
Interrupt Message Format.................................................................... 133
Ignore Numeric Error) .......................................................................... 142
(STPCLK# and CPUSLP#) .................................................................. 143
Intel
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82801EB ICH5 / 82801ER ICH5R Datasheet