FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 257

• Manufacturer Part Number: FW82801EB S L73Z
• Manufacturer: Intel

Specifications of FW82801EB S L73Z

• Lead Free Status / RoHS Status: Not Compliant

5.22.2.4
5.22.2.5
5.22.2.6
5.22.2.7
5.22.2.8
5.22.2.9
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Output Slot 2: Command Data Port
Output Slot 3: PCM Playback Left Channel
Output Slot 4: PCM Playback Right Channel
Output Slot 5: Modem Codec
Output Slot 6: PCM Playback Center Front Channel
In the case of the multiple codec implementation, accesses to the codecs are differentiated by the
driver using address offsets 00h
secondary codec, and address offsets 100h
link, however, is done via the codec ID bits. See Section 6.20.2.23 for further details.
The command data port is used to deliver 16-bit control register write data in the event that the
current command port operation is a write cycle as indicated in slot 1, bit 19. If the current
command port operation is a read, the entire slot time stuffed with 0s by the ICH5. Bits [19:4]
contain the write data. Bits [3:0] are reserved and are stuffed with 0s.
Output frame slot 3 is the composite digital audio left playback stream. Typically, this slot is
composed of standard PCM (.wav) output samples digitally mixed by the host processor. The ICH5
transmits sample streams of 16 bits or 20 bits and stuffs remaining bits with 0s.
Data in output slots 3 and 4 from the ICH5 should be duplicated by software if there is only a single
channel out.
Output frame slot 4 is the composite digital audio right playback stream. Typically, this slot is
composed of standard PCM (.wav) output samples digitally mixed by the host processor. The ICH5
transmits sample streams of 16 or 20 bits and stuffs remaining bits with 0s.
Data in output slots 3 and 4 from the ICH5 should be duplicated by software if there is only a single
channel out.
Output frame slot 5 contains modem DAC data. The modem DAC output supports 16-bit
resolution. At boot time, if the modem codec is supported, the AC ’97 controller driver determines
the DAC resolution. During normal runtime operation the ICH5 stuffs trailing bit positions within
this time slot with 0s.
When set up for 6-channel mode, this slot is used for the front center channel. The format is the
same as Slots 3 and 4. If not set up for 6-channel mode, this channel is always stuffed with 0s by
ICH5.
Output Slots 7–8: PCM Playback Left
and Right Rear Channels
When set up for 4 or 6 channel modes, slots 7 and 8 are used for the rear Left and Right channels.
The format for these two channels are the same as Slots 3 and 4.
–
7Fh for the primary codec, address offsets 80h
–
17Fh for the tertiary codec. The differentiation on the
Functional Description
–
FEh for the
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