FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 531

• Manufacturer Part Number: FW82801EB S L73Z
• Manufacturer: Intel

Specifications of FW82801EB S L73Z

• Lead Free Status / RoHS Status: Not Compliant

14.2.18
14.2.19
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: This register is in the resume well and is reset by RSMRST#.
Note: This register is in the resume well and is reset by RSMRST#.
NOTIFY_DLOW—Notify Data Low Byte Register
(SMBUS—D31:F3)
Register Offset:
Default Value:
NOTIFY_DHIGH—Notify Data High Byte Register
(SMBUS—D31:F3)
Register Offset:
Default Value:
Bit
7:0
Bit
7:0
DATA_HIGH_BYTE — RO. This field contains the second (high) byte of data received during the
Host Notify protocol of the System Management Bus (SMBus) Specification, Version 2.0. Software
should only consider this field valid when the HOST_NOTIFY_STS bit is set to 1.
DATA_LOW_BYTE — RO. This field contains the first (low) byte of data received during the Host
Notify protocol of the System Management Bus (SMBus) Specification, Version 2.0. Software should
only consider this field valid when the HOST_NOTIFY_STS bit is set to 1.
16h
00h
17h
00h
Description
Description
Attribute:
Size:
Attribute:
Size:
SMBus Controller Registers (D31:F3)
RO
8 bits
RO
8 bits
531