FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 516

• Manufacturer Part Number: FW82801EB S L73Z
• Manufacturer: Intel

Specifications of FW82801EB S L73Z

• Lead Free Status / RoHS Status: Not Compliant

SMBus Controller Registers (D31:F3)
14.1.2
14.1.3
516
DID—Device Identification Register
(SMBUS—D31:F3)
Address:
Default Value:
PCICMD—PCI Command Register
(SMBUS—D31:F3)
Address:
Default Value:
15:11
15:0
Bit
Bit
10
9
8
7
6
5
4
3
2
1
0
Reserved
Interrupt Disable — R/W.
0 = Enable
1 = Disables SMBus to assert its PIRQB# signal.
Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
SERR# Enable (SERR_EN) — RO. Hardwired to 0.
Wait Cycle Control (WCC) — RO. Hardwired to 0.
Parity Error Response (PER) — RO. Hardwired to 0.
VGA Palette Snoop (VPS) — RO. Hardwired to 0.
Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Hardwired to 0.
Bus Master Enable (BME) — RO. Hardwired to 0.
Memory Space Enable (MSE) — RO. Hardwired to 0.
I/O Space Enable (IOSE) — R/W.
0 = Disable
1 = Enables access to the SM Bus I/O space registers as defined by the Base Address Register.
Device ID — RO.
02
24D3h
04
0000h
–
–
03h
05h
Description
Intel
Description
Attribute:
Size:
Attributes:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
RO
16 bits
RO, R/W
16 bits