FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 135

• Manufacturer Part Number: FW82801EB S L73Z
• Manufacturer: Intel

Specifications of FW82801EB S L73Z

• Lead Free Status / RoHS Status: Not Compliant

5.10
5.10.1
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: When the IDE primary and secondary controllers are configured for native IDE mode, the only
Serial Interrupt (D31:F0)
The ICH5 supports a serial IRQ scheme. This allows a single signal to be used to report interrupt
requests. The signal used to transmit this information is shared between the host, the ICH5, and all
peripherals that support serial interrupts. The signal line, SERIRQ, is synchronous to PCI clock,
and follows the sustained tri-state protocol that is used by all PCI signals. This means that if a
device has driven SERIRQ low, it will first drive it high synchronous to PCI clock and release it the
following PCI clock. The serial IRQ protocol defines this sustained tri-state signaling in the
following fashion:
The ICH5 supports a message for 21 serial interrupts. These represent the 15 ISA interrupts
(IRQ0–1, 2–15), the four PCI interrupts, and the control signals SMI# and IOCHK#. The serial
IRQ protocol does not support the additional APIC interrupts (20–23).
way to use the internal IRQ14 and IRQ15 connections to the Interrupt controllers is through the
Serial Interrupt pin.
Start Frame
The serial IRQ protocol has two modes of operation which affect the start frame. These two modes
are: Continuous, where the ICH5 is solely responsible for generating the start frame; and Quiet,
where a serial IRQ peripheral is responsible for beginning the start frame.
The mode that must first be entered when enabling the serial IRQ protocol is continuous mode. In
this mode, the ICH5 asserts the start frame. This start frame is 4, 6, or 8 PCI clocks wide based
upon the Serial IRQ Control Register, bits 1:0 at 64h in Device 31:Function 0 configuration space.
This is a polling mode.
When the serial IRQ stream enters quiet mode (signaled in the Stop Frame), the SERIRQ line
remains inactive and pulled up between the Stop and Start Frame until a peripheral drives the
SERIRQ signal low. The ICH5 senses the line low and continues to drive it low for the remainder
of the Start Frame. Since the first PCI clock of the start frame was driven by the peripheral in this
mode, the ICH5 drives the SERIRQ line low for 1 PCI clock less than in continuous mode. This
mode of operation allows for a quiet, and therefore lower power, operation.
•
•
•
S – Sample Phase. Signal driven low
R
T
–
–
Turn-around Phase. Signal released
Recovery Phase. Signal driven high
Functional Description
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