FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 400
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FW82801EB S L73Z
Manufacturer Part Number
FW82801EB S L73Z
Description
Manufacturer
Intel
Datasheet
1.FW82801EB_S_L73Z.pdf
(671 pages)
Specifications of FW82801EB S L73Z
Lead Free Status / RoHS Status
Not Compliant
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- Download datasheet (8Mb)
LPC Interface Bridge Registers (D31:F0)
9.10.10
9.10.11
9.10.12
400
ALT_GP_SMI_EN—Alternate GPI SMI Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
ALT_GP_SMI_STS—Alternate GPI SMI Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
MON_SMI—Device Monitor SMI Status and Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
15:12
15:0
15:0
11:8
Bit
Bit
Bit
7:0
Alternate GPI SMI Enable — R/W. These bits are used to enable the corresponding GPIO to cause
an SMI#. For these bits to have any effect, the following must be true.
Alternate GPI SMI Status — R/WC. These bits report the status of the corresponding GPIs.
0 = Inactive. Software clears this bit by writing a 1 to it.
1 = Active
These bits are sticky. If the following conditions are true, then an SMI# will be generated and the
GPE0_STS bit set:
All bits are in the resume well. Default for these bits is dependent on the state of the GPI pins.
DEV[7:4]_TRAP_STS — R/WC. Bit 12 corresponds to Monitor 4, bit 13 corresponds to Monitor 5
etc.
0 = SMI# was not caused by the associated device monitor. Software clears this bit by writing a 1 to
1 = SMI# was caused by an access to the corresponding device monitor’s I/O range.
DEV[7:4]_TRAP_EN — R/W. Bit 8 corresponds to Monitor 4, bit 9 corresponds to Monitor 5 etc.
0 = Disable
1 = Enables SMI# due to an access to the corresponding device monitor’s I/O range.
Reserved
• The corresponding bit in the ALT_GP_SMI_EN register is set.
• The corresponding GPI must be routed in the GPI_ROUT register to cause an SMI.
• The corresponding GPIO must be implemented.
• The corresponding bit in the ALT_GPI_SMI_EN register is set
• The corresponding GPI must be routed in the GPI_ROUT register to cause an SMI.
• The corresponding GPIO must be implemented.
it.
PMBASE +38h
0000h
No
Resume
PMBASE +3Ah
0000h
No
Resume
PMBASE +40h
0000h
No
Core
Description
Description
Description
Intel
Attribute:
Size:
Usage:
Attribute:
Size:
Usage:
Attribute:
Size:
Usage:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W
16-bit
ACPI or Legacy
R/WC
16-bit
ACPI or Legacy
R/W, R/WC
16-bit
Legacy Only
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