FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 264

• Manufacturer Part Number: FW82801EB S L73Z
• Manufacturer: Intel

Specifications of FW82801EB S L73Z

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.22.4
5.22.5
5.22.6
264
Table 129. AC-link State during PCIRST#
Note: On receipt of wake up signalling from the codec, the digital controller issues an interrupt if
AC ’97 Cold Reset
A cold reset is achieved by asserting AC_RST# for 1 µs. By driving AC_RST# low,
AC_BIT_CLK, and AC_SDOUT will be activated and all codec registers will be initialized to their
default power on reset values. AC_RST# is an asynchronous AC ’97 input to the codec.
AC ’97 Warm Reset
A warm reset re-activates the AC-link without altering the current codec register values. A warm
reset is signaled by driving AC_SYNC high for a minimum of 1 µs in the absence of
AC_BIT_CLK.
Within normal frames, AC_SYNC is a synchronous AC ’97 input to the codec. However, in the
absence of AC_BIT_CLK, AC_SYNC is treated as an asynchronous input to the codec used in the
generation of a warm reset.
The codec must not respond with the activation of AC_BIT_CLK until AC_SYNC has been
sampled low again by the codec. This prevents the false detection of a new frame.
enabled. Software then has to issue a warm or cold reset to the codec by setting the appropriate bit
in the Global Control Register.
System Reset
Table 129
NOTES:
1. ICH5 core well outputs are used as strapping options for the ICH5, sampled during system reset. These
2. The pull-down resistors on these signals are only enabled when the AC-Link Shut Off bit in the AC ’97 Global
3. AC_RST# are held low during S3–S5. It cannot be programmed high during a suspend state.
4. AC_BIT_CLK and AC_SDIN[2:0] are driven low by the codecs during normal states. If the codec is powered
AC_RST#
AC_SDOUT
AC_SYNC
AC_BIT_CLK
AC_SDIN[2:0]
signals may have weak pullups/pulldowns on them. The ICH5 outputs are driven to the appropriate level prior
to AC_RST# being deasserted, preventing a codec from entering test mode. Straps are tied to the core well
to prevent leakage during a suspend state.
Control Register is set to 1. All other times, the pull-down resistor is disabled.
during suspend states it holds these signals low. However, if the codec is not present, or not powered in
suspend, external pull-down resistors are required.
Signal
indicates the states of the link during various system reset and sleep conditions.
Resume
Core
Core
Core
Resume
Power
Plane
1
3
Output
Output
Output
Input
Input
I/O
Driven by codec
Driven by codec
PCIRST#/
During
Low
Low
Low
Intel
®
PCIRST#/
82801EB ICH5 / 82801ER ICH5R Datasheet
Running
Running
Running
Running
After
Low
Cold Reset Bit
Low
Low
Low
Low
(Hi)
S1
2,4
2,4
Low
Low
Low
Low
Low
S3
2,4
2,4
Low
Low
S4/S5
Low
Low
Low
2,4
2,4