NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 343

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

9.7.2
9.7.3
9.7.4
Intel
®
82801DB ICH4 Datasheet
Note: The RTC Index field is write-only for normal operation. This field can only be read in Alt-Access
NMI_EN—NMI Enable (and Real Time Clock Index) Register
I/O Address:
Default Value:
Lockable:
Mode. Note, however, that this register is aliased to Port 74h (documented in
bits are readable at that address.
PORT92—Fast A20 and Init Register
I/O Address:
Default Value:
Lockable:
COPROC_ERR—Coprocessor Error Register
I/O Address:
Default Value:
Lockable:
Bits
Bits
6:0
Bit
7:2
7:0
7
1
0
NMI Enable (NMI_EN) — R/W.
0 = Enable NMI sources.
1 = Disable All NMI sources.
Real Time Clock Index Address (RTC_INDX) — R/W. This data goes to the RTC to select which
register or CMOS RAM address is being accessed.
Reserved
Alternate A20 Gate (ALT_A20_GATE) — R/W. This bit is Or’d with the A20GATE input signal to
generate A20M# to the processor.
0 = A20M# signal can potentially go active.
1 = This bit is set when INIT# goes active.
INIT_NOW — R/W. When this bit transitions from a 0 to a 1, the Intel
for 16 PCI clocks.
COPROC_ERR — WO. Any value written to this register will cause IGNNE# to go active, if FERR#
had generated an internal IRQ13. For FERR# to generate an internal IRQ13, the
COPROC_ERR_EN bit (Device 31:Function 0, Offset D0, Bit 13) must be 1.
70h
80h
No
92h
00h
No
F0h
00h
No
Description
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
®
R/W-Special
8 bit
Core
R/W
8 bit
Core
WO
8 bits
Core
ICH4 will force INIT# active
Table
17-2), and all
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